公开(公告)号：US20060051953A1

公开(公告)日：2006-03-09

申请号：US11263398

申请日：2005-10-31

Applicant: David Corisis ,  Walter Moden ,  Leonard Mess ,  Larry Kinsman

Inventor： David Corisis ,  Walter Moden ,  Leonard Mess ,  Larry Kinsman

IPC: H01L21/44

CPC classification number: H01L24/06 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/145 ,  H05K3/222 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.

Abstract translation: 可堆叠形成高密度组件的球栅阵列封装以及堆叠球栅阵列的方法。 球栅阵列封装包括柔性或刚性衬底。 球栅阵列封装还包括用于连接到半导体器件的电路的阻抗的基本匹配的布置。

公开(公告)号：US20060049504A1

公开(公告)日：2006-03-09

申请号：US11263426

申请日：2005-10-31

Applicant: David Corisis ,  Walter Moden ,  Leonard Mess ,  Larry Kinsman

Inventor： David Corisis ,  Walter Moden ,  Leonard Mess ,  Larry Kinsman

IPC: H01L23/02

CPC classification number: H01L24/06 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/145 ,  H05K3/222 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.

公开(公告)号：US20060033190A1

公开(公告)日：2006-02-16

申请号：US11257428

申请日：2005-10-24

Applicant: Larry Kinsman ,  Walter Moden ,  Warren Farnworth

Inventor： Larry Kinsman ,  Walter Moden ,  Warren Farnworth

IPC: H01L23/02

CPC classification number: H05K3/301 ,  H01L25/105 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K2201/10454 ,  H05K2201/10696 ,  Y10S83/942 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49147 ,  Y10T29/49156 ,  Y10T29/49169 ,  Y10T29/53174 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A semiconductor device package includes a die, a package encapsulating at least a portion of the die, and a plurality of leads. Each lead of the plurality includes an external portion. The external portion of each lead is substantially planar and extends outward from a bottom edge of the package. The external portion of each lead may be oriented in a plane that is substantially parallel to a plane within which the die is located. A semiconductor device including these features may be part of an assembly that also includes an alignment device for orienting the semiconductor device package in nonparallel relation to a substrate.

Abstract translation: 半导体器件封装包括管芯，封装至少一部分裸片的封装以及多个引线。 多个的每个引线包括外部部分。 每个引线的外部部分基本上是平面的并且从封装的底部边缘向外延伸。 每个引线的外部部分可以在基本上平行于管芯所在的平面的平面内取向。 包括这些特征的半导体器件可以是组件的一部分，该组件还包括用于将半导体器件封装以非平行关系定向到衬底的对准装置。

公开(公告)号：US20060001150A1

公开(公告)日：2006-01-05

申请号：US11219134

申请日：2005-09-01

Applicant: Larry Kinsman ,  Walter Moden ,  Warren Farnworth

Inventor： Larry Kinsman ,  Walter Moden ,  Warren Farnworth

IPC: H01L23/48

CPC classification number: H05K3/301 ,  H01L25/105 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K2201/10454 ,  H05K2201/10696 ,  Y10S83/942 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49147 ,  Y10T29/49156 ,  Y10T29/49169 ,  Y10T29/53174 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A semiconductor device including a plurality of stub contacts extending from a single edge thereof. A complementary alignment device includes at least one receptacle for receiving the semiconductor device. The alignment device is securable to a carrier substrate. A contact element may be configured to bias the semiconductor device in such a way as to establish and maintain electrical communication between the semiconductor device and the carrier substrate.

Abstract translation: 一种半导体器件，包括从其单个边缘延伸的多个短截线触点。 互补对准装置包括用于接收半导体器件的至少一个插座。 对准装置可固定到载体基板。 接触元件可以被配置为以这样的方式偏置半导体器件，以便建立和维持半导体器件和载体衬底之间的电连通。

公开(公告)号：US20050287716A1

公开(公告)日：2005-12-29

申请号：US11216965

申请日：2005-08-31

Applicant: Walter Moden ,  Todd Bolken

Inventor： Walter Moden ,  Todd Bolken

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/44

CPC classification number: H01L21/565 ,  H01L23/3121 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A packaged assembly including an interposer or substrate supporting on a first side thereof a chip that is encased with an encapsulant is described. A second side of the interposer or substrate includes a barrier that blocks the flow of encapsulant to create a uniform encapsulant edge on the second side of the interposer. The uniform edge helps prevent flaking of the encapsulant off the interposer. The packaged assembly is adapted to be used with a further electronic device to expand the capablilities of the further electronic device.

Abstract translation: 描述了包括在其第一侧上支撑有封装有密封剂的芯片的插入件或基板的封装组件。 插入器或衬底的第二侧包括阻挡密封剂的流动以在中介层的第二面上产生均匀的密封剂边缘的屏障。 均匀的边缘有助于防止密封剂从中介层剥落。 封装的组件适于与另外的电子设备一起使用以扩展另外的电子设备的可用性。

公开(公告)号：US20050158912A1

公开(公告)日：2005-07-21

申请号：US11040967

申请日：2005-01-21

Applicant: Walter Moden ,  Jerrold King ,  Jerry Brooks

Inventor： Walter Moden ,  Jerrold King ,  Jerry Brooks

IPC: H01L25/10 ,  H01L21/44

CPC classification number: H05K1/181 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/145 ,  H05K1/147 ,  H05K2201/049 ,  H05K2201/10515 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49169 ,  H01L2924/00

Abstract: A low profile multi-IC chip package for high-speed applications comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with buses formed on one side. In another embodiment, the connector comprises multiple buses formed from conductive polymer. In further embodiments, the primary packages are stacked within a cage and have their outer leads in unattached contact with buses within the cage or, alternatively, are directly fixed to leads or pads on the host circuit board.

Abstract translation: 用于高速应用的低调多IC芯片封装包括用于电连接一组堆叠的初级半导体封装的等效外引线的连接器。 在一个实施例中，连接器包括两部分柔性绝缘聚合物片，其一端形成有总线。 在另一个实施例中，连接器包括由导电聚合物形成的多个总线。 在另外的实施例中，初级封装堆叠在保持架内并且使它们的外部引线与保持架内的总线不连接地接触，或者替代地直接固定到主电路板上的引线或焊盘上。

公开(公告)号：US06917090B2

公开(公告)日：2005-07-12

申请号：US10408183

申请日：2003-04-07

Applicant: Walter Moden

Inventor： Walter Moden

IPC: G01R31/02 ,  H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L27/14 ,  H01L27/146

CPC classification number: H01L27/14634 ,  H01L21/563 ,  H01L23/3185 ,  H01L24/28 ,  H01L24/31 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/86 ,  H01L27/14643 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/48747 ,  H01L2224/73203 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83951 ,  H01L2224/8592 ,  H01L2224/92125 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/00014 ,  H01L2224/48744 ,  H01L2924/00

Abstract: A semiconductor package includes a substrate, and a semiconductor die flip chip mounted to the substrate. The package also includes substrate circuitry on a circuit side of the substrate, die circuitry on a back side of the die, terminal contacts on the die circuitry, bonded connections between the substrate circuitry and the die circuitry, and an encapsulant on the bonded connections and edges of the die. The die can include an image sensor on the circuit side configured to receive electromagnetic radiation transmitted through the substrate. A method for fabricating the package includes the step of providing a wafer with multiple dice, forming the die circuitry on the dice, and singulating the wafer into individual dice. The method also includes the steps of providing a substrate panel with multiple substrates, forming the substrate circuitry on the substrates, flip chip bonding the dice to the substrates, forming bonded connections between the dice and the substrates, forming the terminal contacts on the die circuitry, and singulating the panel into separate components.

Abstract translation: 半导体封装包括衬底和安装到衬底的半导体管芯倒装芯片。 封装还包括在衬底的电路侧的衬底电路，裸片的背面上的裸片电路，裸片电路上的端子触点，衬底电路和裸片电路之间的结合连接，以及粘合连接上的密封剂 模具边缘。 芯片可以包括在电路侧的图像传感器，其配置为接收透射通过基板的电磁辐射。 制造封装的方法包括以下步骤：提供具有多个裸片的晶片，在裸片上形成裸片电路，并将晶片分成单独的裸片。 该方法还包括以下步骤：向衬底面板提供多个衬底，在衬底上形成衬底电路，将裸片倒装芯片接合到衬底，在裸片与衬底之间形成接合连接，在裸片电路上形成端子触点 ，并将面板分成单独的组件。

公开(公告)号：US20050146010A1

公开(公告)日：2005-07-07

申请号：US11063403

申请日：2005-02-22

Applicant: Walter Moden ,  David Corisis ,  Leonard Mess ,  Larry Kinsman

Inventor： Walter Moden ,  David Corisis ,  Leonard Mess ,  Larry Kinsman

IPC: H01L23/13 ,  H01L25/10 ,  H01L21/48 ,  H01L23/52

CPC classification number: H01L23/13 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1627 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.

公开(公告)号：US06903465B2

公开(公告)日：2005-06-07

申请号：US09949683

申请日：2001-09-10

Applicant: Warren Farnworth ,  Larry Kinsman ,  Walter Moden

Inventor： Warren Farnworth ,  Larry Kinsman ,  Walter Moden

IPC: H01L23/31 ,  H01L23/528 ,  H01L25/065 ,  H01L23/28

CPC classification number: H01L23/528 ,  H01L23/3171 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A method for packaging a semiconductor device includes connecting a plurality of wire leads to a corresponding plurality of electrical connection pads on the semiconductor device, covering at least a portion of the semiconductor device and at least a portion of each of the wire leads with an encapsulating material, and removing a portion of the encapsulating material and a portion of each of the wire leads to form a packaged semiconductor device wherein each of the wire leads has an exposed portion only at an end. The invention also includes a packaged semiconductor device having an integrated circuit device with a plurality of electrical connection pads, a plurality of wire leads coupled to the plurality of electrical connection pads, and a covering of encapsulating material covering at least a portion of the integrated circuit device and covering each of the wire leads, wherein each of the wire leads has an exposed end. The present invention contemplates wire bonding and encapsulation of individual die as well as multiple die on a single wafer.

Abstract translation: 一种用于封装半导体器件的方法包括将多个引线引线连接到半导体器件上的对应的多个电连接焊盘，覆盖半导体器件的至少一部分以及每个引线的至少一部分具有封装 并且去除所述封装材料的一部分和所述导线引线中的每一个的一部分以形成封装的半导体器件，其中所述引线中的每一个仅在一端具有暴露部分。 本发明还包括具有集成电路器件的封装半导体器件，该集成电路器件具有多个电连接焊盘，耦合到多个电连接焊盘的多个引线引线以及覆盖该集成电路的至少一部分的封装材料的覆盖物 装置并且覆盖每个导线，其中每个导线具有暴露端。 本发明设想在单个晶片上引线接合和封装单个管芯以及多个管芯。

公开(公告)号：US20050003579A1

公开(公告)日：2005-01-06

申请号：US10899258

申请日：2004-07-26

Applicant: Walter Moden

Inventor： Walter Moden

IPC: G01R31/02 ,  H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L27/14 ,  H01L27/146

CPC classification number: H01L27/14634 ,  H01L21/563 ,  H01L23/3185 ,  H01L24/28 ,  H01L24/31 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/86 ,  H01L27/14643 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/48747 ,  H01L2224/73203 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83951 ,  H01L2224/8592 ,  H01L2224/92125 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/00014 ,  H01L2224/48744 ,  H01L2924/00

Abstract: A semiconductor package includes a substrate, and a semiconductor die flip chip mounted to the substrate. The package also includes substrate circuitry on a circuit side of the substrate, die circuitry on a back side of the die, terminal contacts on the die circuitry, bonded connections between the substrate circuitry and the die circuitry, and an encapsulant on the bonded connections and edges of the die. The die can include an image sensor on the circuit side configured to receive electromagnetic radiation transmitted through the substrate. A method for fabricating the package includes the step of providing a wafer with multiple dice, forming the die circuitry on the dice, and singulating the wafer into individual dice. The method also includes the steps of providing a substrate panel with multiple substrates, forming the substrate circuitry on the substrates, flip chip bonding the dice to the substrates, forming bonded connections between the dice and the substrates, forming the terminal contacts on the die circuitry, and singulating the panel into separate components.

Abstract translation: 半导体封装包括衬底和安装到衬底的半导体管芯倒装芯片。 封装还包括在衬底的电路侧上的衬底电路，裸片的背面上的裸片电路，裸片电路上的端子触点，衬底电路和裸片电路之间的结合连接，以及粘合连接上的密封剂 模具边缘。 芯片可以包括在电路侧的图像传感器，其配置为接收透射通过基板的电磁辐射。 制造封装的方法包括以下步骤：提供具有多个裸片的晶片，在裸片上形成裸片电路，并将晶片分成单独的裸片。 该方法还包括以下步骤：向衬底面板提供多个衬底，在衬底上形成衬底电路，将裸片倒装芯片接合到衬底，在裸片与衬底之间形成接合连接，在裸片电路上形成端子触点 ，并将面板分成单独的组件。