公开(公告)号：US20080042252A1

公开(公告)日：2008-02-21

申请号：US11874531

申请日：2007-10-18

Applicant: Walter Moden ,  David Corisis ,  Leonard Mess ,  Larry Kinsman

Inventor： Walter Moden ,  David Corisis ,  Leonard Mess ,  Larry Kinsman

IPC: H01L23/488

CPC classification number: H01L23/13 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1627 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.

Abstract translation: 一种用于球栅阵列半导体器件的高温热应用的装置封装以及包装球栅阵列半导体器件的方法。

公开(公告)号：US20080003712A1

公开(公告)日：2008-01-03

申请号：US11600946

申请日：2006-11-16

Applicant: Walter Moden ,  Jerrold King ,  Jerry Brooks

Inventor： Walter Moden ,  Jerrold King ,  Jerry Brooks

IPC: H01L21/00

CPC classification number: H05K1/181 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/145 ,  H05K1/147 ,  H05K2201/049 ,  H05K2201/10515 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49169 ,  H01L2924/00

Abstract: A method for a low profile multi-IC chip package for high-speed applications comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with buses formed on one side. In another embodiment, the connector comprises multiple buses formed from conductive polymer. In further embodiments, the primary packages are stacked within a cage and have their outer leads in unattached contact with buses within the cage or, alternatively, are directly fixed to leads or pads on the host circuit board.

Abstract translation: 用于高速应用的低轮廓多IC芯片封装的方法包括用于电连接一组堆叠的初级半导体封装的等效外引线的连接器。 在一个实施例中，连接器包括两部分柔性绝缘聚合物片，其一端形成有总线。 在另一个实施例中，连接器包括由导电聚合物形成的多个总线。 在另外的实施例中，初级封装堆叠在保持架内并且使它们的外部引线与保持架内的总线不连接地接触，或者替代地直接固定到主电路板上的引线或焊盘上。

公开(公告)号：US20070115712A1

公开(公告)日：2007-05-24

申请号：US11654435

申请日：2007-01-16

Applicant: Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

Inventor： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

IPC: G11C5/06

CPC classification number: H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

Abstract: The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

Abstract translation: 本发明涉及一种用于形成微电子存储器件的系统，模块以及装置和方法。 在一个实施例中，系统包括处理器和耦合到处理器的控制器，其中至少一个存储器模块耦合到控制器，该模块包括一对存储器件，其相对地定位在衬底的相应表面上并且通过延伸穿过 耦合器件的端子的基板，所述端子被选择为包括被配置为传送功能兼容的信号的一组端子。

公开(公告)号：US20060211174A1

公开(公告)日：2006-09-21

申请号：US11437550

申请日：2006-05-19

Applicant: Walter Moden

Inventor： Walter Moden

IPC: H01L21/00

CPC classification number: H01L24/81 ,  H01L21/485 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5382 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/85 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19107 ,  H05K1/141 ,  H05K3/305 ,  H05K3/328 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/10477 ,  H05K2201/10727 ,  H05K2203/0415 ,  H05K2203/049 ,  Y02P70/613 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead placement arrangement. The board comprises a printed circuit board including first elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the board and the master board, and second elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the semiconductor die and the board. The board has circuit traces for electrical communication between the board/master board electrical contact elements, and the semiconductor die board electrical contact elements.

Abstract translation: 用于将裸半导体管芯与不符合具有特定或标准的引脚输出，连接器焊盘或引线放置布置的主印刷电路板的接合焊盘装置连接的板。 板包括印刷电路板，其包括第一元件，例如用于在基板和母板之间进行电接触的微小焊球，引脚或接合线，以及第二元件，例如微小的焊球，引脚或接合线 用于在半导体管芯和电路板之间进行电接触。 电路板具有用于电路板/主板电接触元件之间的电气通信的电路迹线以及半导体裸片板电接触元件。

公开(公告)号：US20050007807A1

公开(公告)日：2005-01-13

申请号：US10910980

申请日：2004-08-03

Applicant: Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

Inventor： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

IPC: G11C5/00 ,  H05K1/18 ,  G11C7/00

CPC classification number: H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

Abstract: The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

公开(公告)号：US06788547B2

公开(公告)日：2004-09-07

申请号：US10615905

申请日：2003-07-10

Applicant: Walter Moden

Inventor： Walter Moden

IPC: H01R900

CPC classification number: H01R13/2435 ,  H01R13/2442 ,  H01R13/405 ,  H01R43/24 ,  Y10T29/49121 ,  Y10T29/4914 ,  Y10T29/49146 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222 ,  Y10T29/53178 ,  Y10T29/53183

Abstract: The invention provides an electrical contact device, a pre-assembly for producing the electrical contact device, and a method of forming the electrical contact device. The electrical contact device includes a plurality of fine pitch electrical leads disposed in parallel spaced apart relation. An insulating member encapsulates portions of the electrical leads which extend from opposite sides of the insulating member. The insulating member retains the electrical leads in position and electrically isolated from one another. The contact device is used to facilitate connection with the leads of an IC package.

Abstract translation: 本发明提供一种电接触装置，用于制造电接触装置的预组件以及形成电接触装置的方法。 电接触装置包括以平行隔开的关系设置的多个细间距电引线。 绝缘构件封装从绝缘构件的相对侧延伸的电引线的部分。 绝缘构件将电引线保持在适当位置并且彼此电隔离。 该接触装置用于促进与IC封装的引线的连接。

公开(公告)号：US06552427B2

公开(公告)日：2003-04-22

申请号：US10222295

申请日：2002-08-15

Applicant: Walter Moden

Inventor： Walter Moden

IPC: H01L2352

CPC classification number: H01L23/49838 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/4951 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16237 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A BGA package and a method for fabricating the package are provided. The package includes a semiconductor die, internal conductors wire bonded to bond pads on the die, external ball contacts attached to ball bonding pads formed on the conductors in a dense grid pattern, and an encapsulating resin encapsulating the die and conductors. The package is fabricated using a lead frame having lead fingers that form the conductors. The die is back bonded to a polymer tape placed across the lead fingers, and then wire bonded to bonding pads on the conductors. In addition, the encapsulating resin is molded to include openings for the ball contacts which are aligned with the ball bonding pads. An alternate embodiment BGA package includes a polymer substrate adhesively bonded to a face of the die. The polymer substrate includes conductors having beam leads aligned with an opening through the polymer substrate. The opening provides access for a bonding tool for bonding bumps on the beam leads to bond pads on the die.

公开(公告)号：US06232666B1

公开(公告)日：2001-05-15

申请号：US09206116

申请日：1998-12-04

Applicant: David Corisis ,  Walter Moden

Inventor： David Corisis ,  Walter Moden

IPC: H01L2348

CPC classification number: H01L23/49816 ,  H01L24/86 ,  H01L2224/05124 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13164 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: An interconnect for BGA packages, a BGA package fabricated using the interconnect, and a method for fabricating BGA packages using the interconnect, are provided. The interconnect includes multiple polymer substrates on which patterns of conductors are formed. Each substrate can be used to fabricate a BGA package. The conductors on the substrates include end portions having bonding vias formed therethrough in alignment with access openings in the substrates. During fabrication of the BGA packages, the bonding vias allow the conductors to be bonded to bond pads on semiconductor dice by forming metal bumps on the bonding vias and bond pads. The access openings in the substrates provide access to the bonding vias and bond pads for a bonding tool configured to form the metal bumps. In addition to the bonding vias, the conductors include ball bonding pads configured for attaching ball contacts, such as solder balls, to the conductors and substrates. The completed BGA package includes a substrate adhesively bonded to a semiconductor die; conductors with bonding vias on the substrate; metal bumps in the bonding vias bonding the conductors to bond pads on the die; and an area array of ball contacts attached to the conductors and substrate.

公开(公告)号：US07215015B2

公开(公告)日：2007-05-08

申请号：US10899258

申请日：2004-07-26

Applicant: Walter Moden

Inventor： Walter Moden

IPC: H01L23/02

CPC classification number: H01L27/14634 ,  H01L21/563 ,  H01L23/3185 ,  H01L24/28 ,  H01L24/31 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/86 ,  H01L27/14643 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/48747 ,  H01L2224/73203 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83951 ,  H01L2224/8592 ,  H01L2224/92125 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/00014 ,  H01L2224/48744 ,  H01L2924/00

Abstract: A semiconductor package includes a substrate, and a semiconductor die flip chip mounted to the substrate. The package also includes substrate circuitry on a circuit side of the substrate, die circuitry on a back side of the die, terminal contacts on the die circuitry, bonded connections between the substrate circuitry and the die circuitry, and an encapsulant on the bonded connections and edges of the die. The die can include an image sensor on the circuit side configured to receive electromagnetic radiation transmitted through the substrate. A method for fabricating the package includes the step of providing a wafer with multiple dice, forming the die circuitry on the dice, and simulating the wafer into individual dice. The method also includes the steps of providing a substrate panel with multiple substrates, forming the substrate circuitry on the substrates, flip chip bonding the dice to the substrates, forming bonded connections between the dice and the substrates, forming the terminal contacts on the die circuitry, and singulating the panel into separate components.

Abstract translation: 半导体封装包括衬底和安装到衬底的半导体管芯倒装芯片。 封装还包括在衬底的电路侧上的衬底电路，裸片的背面上的裸片电路，裸片电路上的端子触点，衬底电路和裸片电路之间的结合连接，以及粘合连接上的密封剂 模具边缘。 芯片可以包括在电路侧的图像传感器，其配置为接收透射通过基板的电磁辐射。 制造封装的方法包括以下步骤：提供具有多个裸片的晶片，在裸片上形成裸片电路，以及将晶片模拟成单独的裸片。 该方法还包括以下步骤：向衬底面板提供多个衬底，在衬底上形成衬底电路，将裸片倒装芯片接合到衬底，在裸片与衬底之间形成接合连接，在裸片电路上形成端子触点 ，并将面板分成单独的组件。

公开(公告)号：US07065868B2

公开(公告)日：2006-06-27

申请号：US10747333

申请日：2003-12-29

Applicant: Larry Kinsman ,  Mike Brooks ,  Warren M. Farnworth ,  Walter Moden ,  Terry Lee

Inventor： Larry Kinsman ,  Mike Brooks ,  Warren M. Farnworth ,  Walter Moden ,  Terry Lee

IPC: H01R9/00

CPC classification number: H05K7/1415 ,  B25B27/00 ,  H05K3/301 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49169 ,  Y10T29/49208 ,  Y10T29/49222 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183 ,  Y10T29/53191 ,  Y10T29/53209 ,  Y10T29/53257 ,  Y10T29/53261 ,  Y10T29/53265

Abstract: A method is provided for installing circuit components, such as memory devices, in a support, such as a socket. The device to be installed is supported in a holder or shell. The holder is positioned over a support region in the receiving socket. A manual actuator is pressed into the holder to eject the device from the holder and to install the device in the support. The holder may be configured to hold a single device, or multiple devices aligned in slots defined by partitions. A multi-device tray may be provided for indexing devices toward an ejection slot, through which the devices are installed by manual actuation of an ejecting actuator. The technique provides protection for the device prior to and during installation, and facilitates manual installation of such devices without requiring direct hand contact with the device either prior to or during installation.

Abstract translation: 提供了一种用于将电路组件（诸如存储器件）安装在诸如插座的支撑件中的方法。 要安装的设备支撑在支架或外壳中。 保持器定位在接收插座中的支撑区域上方。 将手动执行器压入保持器中以将装置从保持器中排出并将装置安装在支撑件中。 保持器可以被配置为保持单个设备，或者多个设备在由分区定义的槽中对齐。 可以提供多装置托盘用于将装置向分度装置移动到排出槽，通过这些装置通过手动驱动排放致动器来安装装置。 该技术在安装之前和安装期间为设备提供保护，并且便于手动安装这些设备，而不需要在安装之前或安装期间直接与设备接触。