公开(公告)号：US09361421B2

公开(公告)日：2016-06-07

申请号：US14152624

申请日：2014-01-10

Applicant: Altera Corporation

Inventor： David Samuel Goldman ,  Mark Bourgeault ,  Vaughn Betz ,  Alan Louis Herrmann

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5054 ,  G06F17/5072 ,  G06F2217/72

Abstract: A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.

Abstract translation: 用于在目标设备上设计系统的方法包括将目标设备上的资源分配给系统中的静态逻辑模块和部分可重新配置（PR）模块。 其中一个PR模块的实例使用分配的那些资源进行并行布置和路由。 还公开了其他实施例。

公开(公告)号：US20190393878A1

公开(公告)日：2019-12-26

申请号：US16456388

申请日：2019-06-28

Applicant: ALTERA CORPORATION

Inventor： Joshua Walstrom ,  Mark Bourgeault

IPC: H03K19/177 ,  G06F21/60 ,  G06F13/42 ,  G06F13/40 ,  H03K19/0175

Abstract: Systems and methods for generating and deploying integrated circuit (IC) applications are provided. Partial reconfiguration functionality of an IC may be used to build reconfigurable application platforms that enable application execution on the IC. These apps may include partial reconfiguration bitstreams that allow ease of access to programming without cumbersome compilation via a set of complex tools. The apps may be acquired via a purchasing website or other mechanism, where the bitstreams may be downloaded to the IC, thus increasing usability of the IC as well providing addition revenue streams.

公开(公告)号：US09584129B1

公开(公告)日：2017-02-28

申请号：US14310902

申请日：2014-06-20

Applicant: ALTERA CORPORATION

Inventor： Joshua Walstrom ,  Mark Bourgeault

IPC: H03K19/173 ,  H03K19/177 ,  H03K19/0175

CPC classification number: H03K19/17752 ,  H03K19/017581 ,  H03K19/17756

Abstract: Systems and methods for generating and deploying integrated circuit (IC) applications are provided. Partial reconfiguration functionality of an IC may be used to build reconfigurable application platforms that enable application execution on the IC. These apps may include partial reconfiguration bitstreams that allow ease of access to programming without cumbersome compilation via a set of complex tools. The apps may be acquired via a purchasing website or other mechanism, where the bitstreams may be downloaded to the IC, thus increasing usability of the IC as well providing addition revenue streams.

Abstract translation: 提供了用于生成和部署集成电路（IC）应用的系统和方法。 IC的部分重新配置功能可用于构建可重新配置的应用程序平台，使应用程序在IC上执行。 这些应用可以包括部分重配置比特流，其允许通过一组复杂工具轻松访问编程而不需要繁琐的编译。 应用可以通过采购网站或其他机制来获取，其中比特流可以被下载到IC，从而提高IC的可用性以及提供额外的收入流。

公开(公告)号：US08832627B1

公开(公告)日：2014-09-09

申请号：US14010356

申请日：2013-08-26

Applicant: Altera Corporation

Inventor： Mark Bourgeault ,  Ryan Fung ,  David Lewis

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/84 ,  H03K19/00323 ,  H03K19/17736

Abstract: An electronic design automation (EDA) tool alters a user's netlist to provide timing success for distribution of asynchronous signals. Distribution networks are used with the addition of pipeline registers before and/or after the distribution buffer. Or, a tree of pipeline registers is inserted between the asynchronous source and the destination registers. Or, any number of distribution networks are stitched together and pipeline stages may be inserted before and/or after each distribution buffer. Or, beneficial skew is utilized by introducing a delay component that skews a clock signal. The skewed clock signal drives a pipeline register that is inserted before a distribution buffer in order to improve timing margin. Any of various compilation techniques may be used within the EDA tool to solve the problem of distributing high-speed, high-fanout asynchronous signals. The technique has utility for high-performance FPGAs and structured ASIC families, as well as for low-cost FPGAs and other types of logic devices.

Abstract translation: 电子设计自动化（EDA）工具改变用户的网表以提供异步信号分配的时序成功。 分配网络在分配缓冲区之前和/或之后添加流水线寄存器时使用。 或者，在异步源和目标寄存器之间插入一条流水线寄存器树。 或者，任何数量的分发网络被缝合在一起，并且可以在每个分发缓冲器之前和/或之后插入流水线阶段。 或者，通过引入偏移时钟信号的延迟分量来利用有益的偏移。 偏斜时钟信号驱动在分配缓冲器之前插入的流水线寄存器，以便提高定时裕度。 可以在EDA工具中使用各种编译技术中的任何一种来解决分配高速，高扇出异步信号的问题。 该技术可用于高性能FPGA和结构化ASIC系列，以及低成本FPGA和其他类型的逻辑器件。

公开(公告)号：US20140237441A1

公开(公告)日：2014-08-21

申请号：US14152624

申请日：2014-01-10

Applicant: Altera Corporation

Inventor： David Samuel Goldman ,  Mark Bourgeault ,  Vaughn Betz ,  Alan Louis Herrmann

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5054 ,  G06F17/5072 ,  G06F2217/72

Abstract: A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.

Abstract translation: 用于在目标设备上设计系统的方法包括将目标设备上的资源分配给系统中的静态逻辑模块和部分可重新配置（PR）模块。 其中一个PR模块的实例使用分配的那些资源进行并行布置和路由。 还公开了其他实施例。

公开(公告)号：US20210216098A1

公开(公告)日：2021-07-15

申请号：US17214594

申请日：2021-03-26

Applicant: ALTERA CORPORATION

Inventor： Mark Bourgeault

IPC: G06F1/10 ,  G06F1/06 ,  G06F30/331 ,  G06F30/3312 ,  G06F30/392 ,  G06F30/394 ,  H03K19/173 ,  H03L7/07 ,  G06F30/39

Abstract: An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.

公开(公告)号：US10969820B2

公开(公告)日：2021-04-06

申请号：US16415619

申请日：2019-05-17

Applicant: ALTERA CORPORATION

Inventor： Mark Bourgeault

IPC: G06F1/10 ,  H03K19/173 ,  G06F30/39 ,  G06F30/331 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3312 ,  G06F1/06 ,  H03L7/07 ,  H03K3/037

Abstract: An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.

公开(公告)号：US20190251220A1

公开(公告)日：2019-08-15

申请号：US16375620

申请日：2019-04-04

Applicant: Altera Corporation

Inventor： Kevin Chan ,  Mark Bourgeault

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F16/9017 ,  G06F17/5045

Abstract: A method for designing a system on a target device includes identifying portions in the system to preserve based on comparing structural characteristics of the system with another system. Design results from the another system are reused for portions in the system that are preserved.

公开(公告)号：US10374609B1

公开(公告)日：2019-08-06

申请号：US15425744

申请日：2017-02-06

Applicant: ALTERA CORPORATION

Inventor： Joshua Walstrom ,  Mark Bourgeault

IPC: H03K19/173 ,  H03K19/177 ,  H03K19/0175 ,  G06F13/40 ,  G06F13/42 ,  G06F21/60

Abstract: Systems and methods for generating and deploying integrated circuit (IC) applications are provided. Partial reconfiguration functionality of an IC may be used to build reconfigurable application platforms that enable application execution on the IC. These apps may include partial reconfiguration bitstreams that allow ease of access to programming without cumbersome compilation via a set of complex tools. The apps may be acquired via a purchasing website or other mechanism, where the bitstreams may be downloaded to the IC, thus increasing usability of the IC as well providing addition revenue streams.

公开(公告)号：US10242146B2

公开(公告)日：2019-03-26

申请号：US15132163

申请日：2016-04-18

Applicant: Altera Corporation

Inventor： David Samuel Goldman ,  Mark Bourgeault ,  Vaughn Betz ,  Alan Louis Herrmann

IPC: G06F17/50

Abstract: A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.