Integrated device die and package with stress reduction features
    13.
    发明授权
    Integrated device die and package with stress reduction features 有权
    集成器件管芯和封装具有减压特性

    公开(公告)号:US09343367B2

    公开(公告)日:2016-05-17

    申请号:US14577128

    申请日:2014-12-19

    Abstract: An integrated device die and package is disclosed. The integrated device die includes a unitary body. The unitary body can have an upper portion comprising one or more active components. The upper portion can have first and second opposing lateral sides defining at least a portion of a periphery of the upper portion such that an upper surface of the upper portion is disposed between upper edges of the first and second opposing lateral sides. The unitary body can also have a lower portion monolithically formed with the upper portion. The lower portion can comprise a pedestal extending downwardly from the upper portion. The pedestal can be laterally inset from lower edges of the first and second opposing lateral sides. The pedestal can include a distal end portion configured to couple to a carrier.

    Abstract translation: 公开了一种集成器件管芯和封装。 集成器件裸片包括一体式。 整体可以具有包括一个或多个活性组分的上部部分。 上部可以具有限定上部的周边的至少一部分的第一和第二相对侧边,使得上部的上表面设置在第一和第二相对的侧面的上边缘之间。 整体也可以具有与上部一体地形成的下部。 下部可以包括从上部向下延伸的基座。 基座可以从第一和第二相对侧面的下边缘侧向插入。 基座可以包括配置成联接到托架的远端部分。

    VERTICAL MOUNT PACKAGE AND WAFER LEVEL PACKAGING THEREFOR
    14.
    发明申请
    VERTICAL MOUNT PACKAGE AND WAFER LEVEL PACKAGING THEREFOR 审中-公开
    垂直安装包装及其水平包装

    公开(公告)号:US20140374854A1

    公开(公告)日:2014-12-25

    申请号:US14484151

    申请日:2014-09-11

    Inventor: Xiaojie Xue

    Abstract: Vertical mount packages and methods for making the same are disclosed. A method for manufacturing a vertical mount package includes providing a device substrate with a plurality of device regions on a front surface, and a plurality of through-wafer vias. MEMS devices or integrated circuits are formed or mounted onto the device regions. A capping substrate having recesses is mounted over the device substrate, enclosing the device regions within cavities defined by the recesses. A plurality of aligned through-wafer contacts extend through the capping substrate and the device substrate. The device substrate and capping substrate can be singulated by cutting through the aligned through-wafer contacts, with the severed through-wafer contacts forming vertical mount leads. A vertical mount package includes a device sealed between a device substrate and a capping substrate. At least of the side edges of the package includes exposed conductive elements for vertical mount leads.

    Abstract translation: 公开了垂直安装封装及其制造方法。 一种用于制造垂直安装封装的方法包括:在前表面上提供具有多个器件区域的器件基板,以及多个贯通晶片通孔。 MEMS器件或集成电路形成或安装到器件区域上。 具有凹槽的封盖基板安装在器件基板上,将器件区域包围在由凹槽限定的空腔内。 多个对准的跨晶片触点延伸穿过封盖衬底和器件衬底。 可以通过切割对准的通过晶片的触点来切割器件衬底和封盖衬底,切断的晶片接触件形成垂直安装引线。 垂直安装封装包括密封在器件基板和封盖基板之间的器件。 封装的至少侧边缘包括用于垂直安装引线的露出的导电元件。

Patent Agency Ranking