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    BIAS TEMPERATURE INSTABILITY CORRECTION IN MEMORY ARRAYS
    11.
    发明申请
    BIAS TEMPERATURE INSTABILITY CORRECTION IN MEMORY ARRAYS 有权

    公开(公告)号：US20230058423A1

    公开(公告)日：2023-02-23

    申请号：US17408429

    申请日：2021-08-22

    Applicant: Applied Materials, Inc.

    Inventor： Christophe J. Chevallier ,  Siddarth Krishnan

    IPC: G11C13/00 ,  G11C11/16

    Abstract: A method of correcting bias temperature instability in memory arrays may include applying a first bias to a memory cell, where the memory cell may include a memory element and a select element, and the first bias may causes a value to be stored in the memory element. The first bias causes a bias temperature instability (BTI) associated with the memory cell to increase. The method may also include applying a second bias to the memory cell, where the second bias may have a polarity that is opposite of the first bias, and the value stored in the memory element remains in the memory element after the second bias is applied. The second bias may also cause the BTI associated with the memory cell to decrease while maintaining any value stored in the memory cell.

    Power device structures and methods of making
    15.
    发明授权
    Power device structures and methods of making 有权

    公开(公告)号：US11769665B2

    公开(公告)日：2023-09-26

    申请号：US17572963

    申请日：2022-01-11

    Applicant: Applied Materials, Inc.

    Inventor： Amirhasan Nourbakhsh ,  Raman Gaire ,  Tyler Sherwood ,  Lan Yu ,  Roger Quon ,  Siddarth Krishnan

    IPC: H01L21/02

    CPC classification number: H01L21/02576 ,  H01L21/02532 ,  H01L21/02579

    Abstract: Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.

    Dual oxide analog switch for neuromorphic switching
    16.
    发明授权
    Dual oxide analog switch for neuromorphic switching 有权

    公开(公告)号：US11616195B2

    公开(公告)日：2023-03-28

    申请号：US16883009

    申请日：2020-05-26

    Applicant: Applied Materials, Inc.

    Inventor： Deepak Kamalanathan ,  Archana Kumar ,  Siddarth Krishnan

    IPC: H01L45/00

    Abstract: Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.

    SOFT RESET FOR MULTI-LEVEL PROGRAMMING OF MEMORY CELLS IN NON-VON NEUMANN ARCHITECTURES
    17.
    发明申请
    SOFT RESET FOR MULTI-LEVEL PROGRAMMING OF MEMORY CELLS IN NON-VON NEUMANN ARCHITECTURES 有权

    公开(公告)号：US20210280247A1

    公开(公告)日：2021-09-09

    申请号：US17329008

    申请日：2021-05-24

    Applicant: Applied Materials, Inc.

    Inventor： Deepak Kamalanathan ,  Siddarth Krishnan ,  Archana Kumar ,  Fuxi Cai ,  Federico Nardi

    IPC: G11C13/00

    Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.

    Soft reset for multi-level programming of memory cells in non-Von Neumann architectures
    18.
    发明授权
    Soft reset for multi-level programming of memory cells in non-Von Neumann architectures 有权

    公开(公告)号：US11017856B1

    公开(公告)日：2021-05-25

    申请号：US16793794

    申请日：2020-02-18

    Applicant: Applied Materials, Inc.

    Inventor： Deepak Kamalanathan ,  Siddarth Krishnan ,  Archana Kumar ,  Fuxi Cai ,  Federico Nardi

    IPC: G11C11/00 ,  G11C13/00

    Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.

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