公开(公告)号：US11946157B2

公开(公告)日：2024-04-02

申请号：US17743039

申请日：2022-05-12

Applicant: ASM IP Holding B.V.

Inventor： Rami Khazaka ,  Qi Xie

IPC: C30B25/10 ,  C30B29/06 ,  C30B29/08 ,  C30B33/12

CPC classification number: C30B25/10 ,  C30B29/06 ,  C30B29/08 ,  C30B33/12

Abstract: Methods and devices for epitaxially growing boron doped silicon germanium layers. The layers may be used, for example, as a p-type source and/or drain regions in field effect transistors.

公开(公告)号：US20240096619A1

公开(公告)日：2024-03-21

申请号：US18307489

申请日：2023-04-26

Applicant: ASM IP Holding, B.V.

Inventor： Brendan Timothy Padraig Marozas ,  Rami Khazaka

IPC: H01L21/02 ,  H01L21/3065

CPC classification number: H01L21/02579 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/3065

Abstract: Methods and systems for selectively forming phosphorus-doped epitaxial material. The methods can be used to selectively form the phosphorus-doped epitaxial material within a gap from the bottom upward. Exemplary methods can be used to, for example, form source and/or drain regions in field effect transistor devices, such as in gate-all-around field effect transistor devices.

公开(公告)号：US11646205B2

公开(公告)日：2023-05-09

申请号：US17071149

申请日：2020-10-15

Applicant: ASM IP Holding B.V.

Inventor： Rami Khazaka ,  Lucas Petersen Barbosa Lima ,  Giuseppe Alessio Verni ,  Qi Xie

IPC: H01L21/02 ,  H01L21/306 ,  H01L29/36 ,  C23C16/52 ,  H01L21/67

CPC classification number: H01L21/02636 ,  C23C16/52 ,  H01L21/30604 ,  H01L21/67063 ,  H01L29/36

Abstract: A method for selectively forming an n-type doped material on a surface of a substrate is disclosed. A system for performing the method and structures and devices formed using the method are also disclosed.

公开(公告)号：US20220364262A1

公开(公告)日：2022-11-17

申请号：US17743039

申请日：2022-05-12

Applicant: ASM IP Holding B.V.

Inventor： Rami Khazaka ,  Qi Xie

IPC: C30B25/10 ,  C30B33/12 ,  C30B29/08 ,  C30B29/06

Abstract: Methods and devices for epitaxially growing boron doped silicon germanium layers. The layers may be used, for example, as a p-type source and/or drain regions in field effect transistors.

公开(公告)号：US20210254238A1

公开(公告)日：2021-08-19

申请号：US17166160

申请日：2021-02-03

Applicant: ASM IP Holding B.V.

Inventor： Rami Khazaka ,  Lucas Petersen Barbosa Lima ,  Qi Xie

IPC: C30B29/06 ,  C30B31/10 ,  C30B23/02 ,  C30B31/18 ,  C30B23/00

Abstract: Methods and devices for low-temperature deposition of phosphorous-doped silicon layers. Disilane is used as a silicon precursor, and nitrogen or a noble gas is used as a carrier gas. Phosphine is a suitable phosphorous precursor.

公开(公告)号：US20240379353A1

公开(公告)日：2024-11-14

申请号：US18659368

申请日：2024-05-09

Applicant: ASM IP Holding B.V.

Inventor： Wonjong Kim ,  Rami Khazaka

IPC: H01L21/02 ,  C30B25/02

Abstract: A method for epitaxially forming an epitaxial stack on a substrate is disclosed. Embodiments of the presently described method comprise performing a plurality of deposition cycles to form the epitaxial stack, whereby each of the deposition cycles comprises deposition pulses to form the individual epitaxial layers of the epitaxial stack.

公开(公告)号：US20240203734A1

公开(公告)日：2024-06-20

申请号：US18540329

申请日：2023-12-14

Applicant: ASM IP Holding B.V.

Inventor： Maritza Mujica ,  Ernesto Suarez ,  Amir Kajbafvala ,  Rami Khazaka ,  Arum Murali ,  Frederick Aryeetey ,  Yanfu Lu ,  Caleb Miskin ,  Alexandros Demos ,  Bibek Karki

IPC: H01L21/02 ,  C30B25/10 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  H01L29/78

CPC classification number: H01L21/0262 ,  C30B25/10 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/7848 ,  H01L29/167

Abstract: Methods for forming multilayer structures are disclosed. The methods may include, seating a substrate within a chamber body, and regulating a temperature profile across an upper surface of the substrate during each individual deposition phase of multiphase deposition process. Semiconductor device structures including multilayer structures are also disclosed.

公开(公告)号：US20240087888A1

公开(公告)日：2024-03-14

申请号：US18465835

申请日：2023-09-12

Applicant: ASM IP Holding, B.V.

Inventor： Rami Khazaka

IPC: H01L21/02 ,  C30B25/10 ,  H01L21/3065

CPC classification number: H01L21/02532 ,  C30B25/10 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065

Abstract: A method for forming a Si-comprising epitaxial layer selectively on a substrate is disclosed. Embodiments of the presently described method comprise performing a cyclic deposition and etch processes, thereby forming selectively the Si-comprising epitaxial layer. The described method may help to form source/drain regions of field effect transistors in a bottom-up manner.

公开(公告)号：US20240006176A1

公开(公告)日：2024-01-04

申请号：US18214656

申请日：2023-06-27

Applicant: ASM IP Holding B.V.

Inventor： Lucas Petersen Barbosa Lima ,  Charles Dezelah ,  Rami Khazaka ,  Qi Xie ,  Giuseppe Alessio Verni

IPC: H01L21/02 ,  C30B29/52 ,  C30B25/02

CPC classification number: H01L21/0262 ,  H01L21/02532 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02579

Abstract: Methods and systems for forming a p-type doped silicon germanium layer. The p-type doped silicon germanium layer can include silicon, germanium, gallium, and, in at least some cases, indium.

公开(公告)号：US20230352301A1

公开(公告)日：2023-11-02

申请号：US18304125

申请日：2023-04-20

Applicant: ASM IP Holding, B.V.

Inventor： Rami Khazaka

IPC: H01L21/02 ,  C30B25/18 ,  C30B29/52 ,  C30B33/08 ,  C30B31/06 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/786 ,  H01L21/3065

CPC classification number: H01L21/02532 ,  C30B25/18 ,  C30B29/52 ,  C30B33/08 ,  C30B31/06 ,  H01L29/42392 ,  H01L29/0669 ,  H01L29/66439 ,  H01L29/0847 ,  H01L29/78681 ,  H01L21/02433 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/3065

Abstract: Methods and systems for selectively forming crystalline boron-doped silicon germanium on a surface of a substrate. The methods can be used to selectively form the boron-doped silicon germanium within a gap from the bottom upward. Exemplary methods can be used to, for example, form source and/or drain regions in field effect transistor devices, such as in gate-all-around field effect transistor devices.