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    SYSTEMS AND METHODS FOR CLEANING A PORTION OF A LITHOGRAPHY APPARATUS
    11.
    发明申请
    SYSTEMS AND METHODS FOR CLEANING A PORTION OF A LITHOGRAPHY APPARATUS 有权

    公开(公告)号：US20250138441A1

    公开(公告)日：2025-05-01

    申请号：US18837353

    申请日：2023-01-24

    Applicant: ASML NETHERLANDS B.V.

    Inventor： Tammo UITTERDIJK ,  Ankur Ramesh BAHETI ,  Christopher SCHROECK

    IPC: G03F7/00

    Abstract: A system for cleaning contamination particles from a clamp of a lithography apparatus. The system includes a body configured to be inserted into the lithography apparatus, engaged by a tool handler of the lithography apparatus, and positioned by the tool handler for clamping by the clamp. Cleaning features are patterned on a clamp facing surface of the body. Locations and dimensions of the cleaning features on the clamp facing surface approximate locations and dimensions of the contamination particles on the clamp, such that relative movement between the cleaning features and the clamp cleans the contamination particles from the clamp. For example, the locations of the cleaning features on the clamp facing surface can correspond to object contact areas (e.g., burls) on the clamp where the contamination particles are located. The dimensions of the cleaning features comprise a specific pitch, a line width, and a thickness.

    WAFER CLAMP HARD BURL PRODUCTION AND REFURBISHMENT
    12.
    发明申请
    WAFER CLAMP HARD BURL PRODUCTION AND REFURBISHMENT 有权

    公开(公告)号：US20230031443A1

    公开(公告)日：2023-02-02

    申请号：US17788806

    申请日：2020-12-08

    Applicant: ASML Holding N.V.

    Inventor： Matthew LIPSON ,  Mehmet Ali AKBAS ,  Tammo UITTERDIJK ,  Fei ZHAO

    IPC: G03F7/20

    Abstract: Systems, apparatuses, and methods are provided for manufacturing a wafer clamp having hard burls. The method can include providing a first layer that includes a first surface. The method can further include forming a plurality of burls over the first surface of the first layer. The forming of the plurality of burls can include forming a subset of the plurality of burls to a hardness of greater than about 6.0 gigapascals (GPa).

    SUB MICRON PARTICLE DETECTION ON BURL TOPS BY APPLYING A VARIABLE VOLTAGE TO AN OXIDIZED WAFER
    13.
    发明公开
    SUB MICRON PARTICLE DETECTION ON BURL TOPS BY APPLYING A VARIABLE VOLTAGE TO AN OXIDIZED WAFER 审中-公开

    公开(公告)号：US20230314962A1

    公开(公告)日：2023-10-05

    申请号：US18012317

    申请日：2021-06-04

    Applicant: ASML Holding N.V.

    Inventor： Tammo UITTERDIJK

    IPC: G03F7/20 ,  H01L21/67 ,  H01L21/683

    CPC classification number: G03F7/70783 ,  G03F7/70708 ,  H01L21/67288 ,  H01L21/6831

    Abstract: Systems, apparatuses, methods, and computer program products are provided for determining a free form flatness of a substrate table. An example system can include a substrate table that includes a first substrate table surface and a grounded substrate table electrical connection configured to ground the substrate table. The system can further include a substrate that includes a semiconducting layer, a thermally-grown insulating layer, a first substrate surface disposed on the insulating layer, and a substrate electrical connection configured to transmit a voltage to the semiconducting layer. The system can further include a metrology system configured to apply a voltage to the substrate electrical connection to electrostatically clamp the substrate to the substrate table, measure a flatness of the first substrate surface, and determine a free form flatness of the first substrate table surface based on the measured flatness of the first substrate surface.

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