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    Vertical GaN power device with breakdown voltage control
    12.
    发明授权
    Vertical GaN power device with breakdown voltage control 有权
    垂直GaN功率器件具有击穿电压控制

    公开(公告)号：US08866148B2

    公开(公告)日：2014-10-21

    申请号：US13721542

    申请日：2012-12-20

    Applicant: Avogy, Inc.

    Inventor： Donald R. Disney

    IPC: H01L29/207 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L29/0619 ,  H01L21/26546 ,  H01L29/0615 ,  H01L29/0626 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/66909 ,  H01L29/66924 ,  H01L29/8083 ,  H01L29/8613 ,  H01L29/872

    Abstract: A method for fabricating a vertical GaN power device includes providing a first GaN material having a first conductivity type and forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a junction. The method further includes implanting ions through the second GaN material and into a first portion of the first GaN material to increase a doping concentration of the first conductivity type. The first portion of the junction is characterized by a reduced breakdown voltage relative to a breakdown voltage of a second portion of the junction.

    Abstract translation: 制造垂直GaN功率器件的方法包括：提供具有第一导电类型的第一GaN材料，并形成具有第二导电类型的第二GaN材料并与第一GaN材料耦合以形成结。 该方法还包括将离子注入第二GaN材料并进入第一GaN材料的第一部分以增加第一导电类型的掺杂浓度。 结的第一部分的特征在于相对于结的第二部分的击穿电压降低的击穿电压。

    VERTICAL GALLIUM NITRIDE JFET WITH GATE AND SOURCE ELECTRODES ON REGROWN GATE
    13.
    发明申请
    VERTICAL GALLIUM NITRIDE JFET WITH GATE AND SOURCE ELECTRODES ON REGROWN GATE 有权
    带门和源电极的垂直栅极栅极

    公开(公告)号：US20140291691A1

    公开(公告)日：2014-10-02

    申请号：US14192662

    申请日：2014-02-27

    Applicant: Avogy, Inc.

    Inventor： Donald R. Disney ,  Hui Nie ,  Isik C. Kizilyalli ,  Richard J. Brown

    IPC: H01L29/808 ,  H01L29/66 ,  H01L29/20

    CPC classification number: H01L29/8083 ,  H01L29/0623 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/66909 ,  H01L29/66924

    Abstract: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.

    Abstract translation: 半导体结构包括具有第一表面和第二表面的GaN衬底。 GaN衬底的特征在于第一导电类型和第一掺杂剂浓度。 第一电极电耦合到GaN衬底的第二表面。 半导体结构还包括耦合到GaN衬底的第一表面的第一导电类型的第一GaN外延层和耦合到第一GaN外延层的第二导电类型的第二GaN层。 第一GaN外延层包括沟道区。 第二GaN外延层包括栅极区域和边缘端接结构。 耦合到栅极区域的第二电极和耦合到沟道区域的第三电极都设置在边缘端接结构内。

    METHOD AND SYSTEM FOR FABRICATING FLOATING GUARD RINGS IN GAN MATERIALS
    14.
    发明申请
    METHOD AND SYSTEM FOR FABRICATING FLOATING GUARD RINGS IN GAN MATERIALS 有权
    用于制造烟草材料中浮动护栏的方法和系统

    公开(公告)号：US20140235030A1

    公开(公告)日：2014-08-21

    申请号：US14264998

    申请日：2014-04-29

    Applicant: AVOGY, INC.

    Inventor： Donald R. Disney ,  Andrew P. Edwards ,  Hui Nie ,  Richard J. Brown ,  Isik C. Kizilyalli ,  David P. Bour ,  Linda Romano ,  Thomas R. Prunty

    IPC: H01L21/761 ,  H01L21/765

    CPC classification number: H01L21/761 ,  H01L21/2654 ,  H01L21/266 ,  H01L21/765 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66136 ,  H01L29/66212 ,  H01L29/6631 ,  H01L29/66909 ,  H01L29/8083 ,  H01L29/872

    Abstract: A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.

    Abstract translation: 一种用于制造边缘终端结构的方法包括提供具有第一表面和第二表面和第一导电类型的衬底，形成耦合到衬底的第一表面的第一导电类型的第一GaN外延层，并形成第二 与第一导电类型相反的第二导电类型的GaN外延层。 第二GaN外延层耦合到第一GaN外延层。 该方法还包括将离子注入第二GaN外延层的第一区域以将第二GaN外延层的第二区域与第二GaN外延层的第三区域电隔离。 该方法还包括形成耦合到第二GaN外延层的第二区域并形成耦合到第二GaN外延层的第三区域的边缘端接结构的有源器件。

    Method of fabricating a GaN P-i-N diode using implantation
    15.
    发明授权
    Method of fabricating a GaN P-i-N diode using implantation 有权
    使用注入制造GaN P-i-N二极管的方法

    公开(公告)号：US09484470B2

    公开(公告)日：2016-11-01

    申请号：US14834306

    申请日：2015-08-24

    Applicant: Avogy, Inc.

    Inventor： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Richard J. Brown ,  Donald R. Disney

    IPC: H01L29/868 ,  H01L29/06 ,  H01L21/20 ,  H01L29/66 ,  H01L29/20

    CPC classification number: H01L29/868 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/66204 ,  H01L29/66212 ,  H01L29/6631 ,  H01L29/66924

    Abstract: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region

    Abstract translation: III族氮化物半导体器件包括用于在III族氮化物半导体器件的正向偏置操作期间支持电流的有源区域。 有源区包括具有第一导电类型的第一III族氮化物外延材料和具有第二导电类型的第二III族氮化物外延材料。 III族氮化物半导体器件还包括物理地邻近有源区的边缘终端区，并且包括包含第一III族氮化物外延材料的一部分的注入区。 第一III族氮化物外延材料的注入区域相对于邻近于注入区域的第一III族氮化物外延材料的部分具有降低的导电性

    GALLIUM NITRIDE VERTICAL JFET WITH HEXAGONAL CELL STRUCTURE
    20.
    发明申请
    GALLIUM NITRIDE VERTICAL JFET WITH HEXAGONAL CELL STRUCTURE 审中-公开
    具有六角形细胞结构的硝酸锌垂直JFET

    公开(公告)号：US20140191241A1

    公开(公告)日：2014-07-10

    申请号：US13735897

    申请日：2013-01-07

    Applicant: AVOGY, INC.

    Inventor： Andrew P. Edwards ,  Hui Nie ,  Donald R. Disney ,  Isik Kizilyalli

    IPC: H01L27/098

    CPC classification number: H01L27/098 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/42312 ,  H01L29/66909 ,  H01L29/8083

    Abstract: An array of GaN-based vertical JFETs includes a GaN substrate comprising a drain of one or more of the JFETs and one or more epitaxial layers coupled to the GaN substrate. The array also includes a plurality of hexagonal cells coupled to the one or more epitaxial layers and extending in a direction normal to the GaN substrate. Sidewalls of the plurality of hexagonal cells are substantially aligned with respect to crystal planes of the GaN substrate. The array further includes a plurality of channel regions, each having a portion adjacent a sidewall of the plurality of hexagonal cells, a plurality of gate regions of one or more of the JFETs, each electrically coupled to one or more of the plurality of channel regions, and a plurality of source regions of one or more of the JFETs electrically coupled to one or more of the plurality of channel regions.

    Abstract translation: GaN基垂直JFET的阵列包括包含一个或多个JFET的漏极和耦合到GaN衬底的一个或多个外延层的GaN衬底。 该阵列还包括耦合到一个或多个外延层并沿垂直于GaN衬底的方向延伸的多个六边形单元。 多个六边形单元的侧壁相对于GaN衬底的晶面基本上对齐。 阵列还包括多个通道区域，每个沟道区域具有邻近多个六边形单元的侧壁的部分，一个或多个JFET的多个栅极区域，每个栅极区域电耦合到多个沟道区域中的一个或多个 以及电耦合到多个沟道区中的一个或多个的一个或多个JFET的多个源极区。

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