公开(公告)号：US20240105675A1

公开(公告)日：2024-03-28

申请号：US17936167

申请日：2022-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz ,  John J. Wuu

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/528 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/5386

Abstract: An apparatus and method for efficiently routing power signals across semiconductor dies. A semiconductor fabrication process (or process) places a first semiconductor die in an integrated circuit and stacks a second semiconductor die vertically adjacent to the first semiconductor die. The process forms multiple backside metal layers vertically adjacent to a backside of a silicon substrate of the second semiconductor die. The process forms a first backside metal layer that includes at least a first power route that forms a rectangle within the first backside metal layer. The process forms a second backside metal layer that includes at least a second power rail that forms an L-shape within the second backside metal layer. The process connects one or more corners of the rectangle of the first power rail to a corresponding corner of a separate power rail of the second backside metal layer that forms an L-shape.

公开(公告)号：US11710698B2

公开(公告)日：2023-07-25

申请号：US17030821

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Richard T. Schultz

IPC: H01L23/528 ,  H01L27/11 ,  H01L23/522 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  G11C11/418 ,  G11C11/419 ,  H10B10/00

CPC classification number: H01L23/528 ,  G11C11/418 ,  G11C11/419 ,  H01L23/5226 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H10B10/125 ,  H10B10/18

Abstract: A layout for a 6T SRAM cell array is disclosed. The layout doubles the number of bits per bit cell in the array by implementing dual pairs of bitlines spanning bit cell columns in the array. Alternating connections (e.g., alternating vias) may be provided for wordline access to the bitlines in the layout. Alternating the connections may reduce RC delay in the layout.

公开(公告)号：US20220415378A1

公开(公告)日：2022-12-29

申请号：US17359446

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Arijit Banerjee ,  John J. Wuu ,  Russell Schreiber

IPC: G11C8/16 ,  G06F30/392 ,  G11C11/419 ,  G11C11/418

Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. Adjacent bit cells in a column of an array use a split read port such that the bit cells do not share a read bit line while sharing a write bit line. The adjacent bit cells include asymmetrical read access circuits that convey data stored by latch circuitry of a corresponding bit cell to a corresponding read bit line. The layout of adjacent bit cells provides a number of contacted gate pitches per bit cell that is less than a sum of the maximum number of metal gates in layout of each of the adjacent bit cells divided by the number of adjacent bit cells.

公开(公告)号：US20220366945A1

公开(公告)日：2022-11-17

申请号：US17359253

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Russell J. Schreiber

IPC: G11C7/10 ,  G11C7/12 ,  H03K19/173

Abstract: A static random access memory (SRAM) includes fast SRAM bit cells and fast multiplexer circuits that are formed in a first row of fast cells in a hybrid standard cell architecture. Slow SRAM bit cells and slow multiplexer circuits are formed in a second row of slow cells. The slow multiplexer circuits provide a column output for the fast SRAM bit cells and the fast multiplexer circuits provide a column output for the slow SRAM bit cells. Thus, one SRAM column has fast bit cells and slow multiplexer stages while the adjacent SRAM column has slow bit cells and fast multiplexer stages to thereby provide an improved performance balance when reading the SRAM.

公开(公告)号：US20220093503A1

公开(公告)日：2022-03-24

申请号：US17030821

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Richard T. Schultz

IPC: H01L23/528 ,  H01L27/11 ,  H01L23/522 ,  G11C11/418 ,  G11C11/419 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A layout for a 6T SRAM cell array is disclosed. The layout doubles the number of bits per bit cell in the array by implementing dual pairs of bitlines spanning bit cell columns in the array. Alternating connections (e.g., alternating vias) may be provided for wordline access to the bitlines in the layout. Alternating the connections may reduce RC delay in the layout.

公开(公告)号：US09575891B2

公开(公告)日：2017-02-21

申请号：US14307164

申请日：2014-06-17

Applicant: Advanced Micro Devices, Inc.

Inventor： John R. Riley ,  Russell Schreiber ,  Donald R. Weiss ,  John J. Wuu ,  William A. McGee

IPC: G06F12/00 ,  G06F12/06 ,  G11C5/02

CPC classification number: G06F12/0607 ,  G06F12/0623 ,  G06F2212/1052 ,  G06F2212/2532 ,  G11C5/025

Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M−A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle.

Abstract translation: 用于布局规划存储器的系统和方法。 计算系统包括生成存储器访问请求的处理单元和存储器。 存储器中每个存储器线的大小包括M位。 记忆体至少包括一个主要银行和一个侧边银行。 主存储体包括第一部分，存取存储器线的M位的（M-A）位。 旁边组包括存取线的M位的A位的第二部分。 主要银行和旁边银行的高度相同，如果主存储包含每个存储行中的所有M位，则低于要使用的高度。 对于存储器线路的M位的访问请求的完成在类似的时间完成，例如相同的时钟周期。

公开(公告)号：US20150364168A1

公开(公告)日：2015-12-17

申请号：US14307164

申请日：2014-06-17

Applicant: Advanced Micro Devices, Inc.

Inventor： John R. Riley ,  Russell Schreiber ,  Donald R. Weiss ,  John J. Wuu ,  William A. McGee

IPC: G11C7/18 ,  G11C11/406 ,  G06F12/06

CPC classification number: G06F12/0607 ,  G06F12/0623 ,  G06F2212/1052 ,  G06F2212/2532 ,  G11C5/025

Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M−A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle.

Abstract translation: 用于布局规划存储器的系统和方法。 计算系统包括生成存储器访问请求的处理单元和存储器。 存储器中每个存储器线的大小包括M位。 记忆体至少包括一个主要银行和一个侧边银行。 主存储体包括第一部分，存取存储器线的M位的（M-A）位。 旁边组包括存取线的M位的A位的第二部分。 主要银行和旁边银行的高度相同，如果主存储包含每个存储行中的所有M位，则低于要使用的高度。 对于存储器线路的M位的访问请求的完成在类似的时间完成，例如相同的时钟周期。

公开(公告)号：US08958236B2

公开(公告)日：2015-02-17

申请号：US13749672

申请日：2013-01-24

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Keith A. Kasprak ,  Russell Schreiber

IPC: G11C7/00 ,  G11C11/412 ,  G11C7/04

CPC classification number: G11C11/412 ,  G11C7/04

Abstract: An apparatus may comprise a memory cell configured to operate according to a voltage mode, a voltage controller coupled with the memory cell, wherein the voltage controller is configured to change the voltage mode of the memory cell between a low voltage mode and a high voltage mode, and a memory controller module coupled with the memory cell, wherein the memory controller is configured to invert a logic state stored in the memory cell based on the voltage mode.

Abstract translation: 装置可以包括被配置为根据电压模式操作的存储单元，与存储单元耦合的电压控制器，其中电压控制器被配置为在低电压模式和高电压模式之间改变存储单元的电压模式 以及与所述存储器单元耦合的存储器控​​制器模块，其中所述存储器控制器被配置为基于所述电压模式反转存储在所述存储器单元中的逻辑状态。

公开(公告)号：US20130069964A1

公开(公告)日：2013-03-21

申请号：US13623937

申请日：2012-09-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John J. Wuu ,  Donald R. Weiss

IPC: G06T1/60 ,  H01L21/8239 ,  G11C11/34

CPC classification number: G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/0061 ,  G11C14/0081 ,  G11C14/009 ,  G11C2213/77

Abstract: A method, integrated circuit and apparatus are operative to control a plurality of passive variable resistance memory cells to store complimentary state information from at least one active memory circuit, such as a flop, latch, or any other suitable state generation circuit. The method, apparatus and integrated circuit may be operative to control the plurality of passive variable resistance memory cells to also restore the stored complimentary state information for the at least one active memory.

Abstract translation: 一种方法，集成电路和装置可操作以控制多个可变电阻存储器单元以从至少一个有效存储器电路（诸如触发器，锁存器或任何其它合适的状态产生电路）存储互补状态信息。 该方法，装置和集成电路可操作以控制多个可变电阻存储器单元，以还恢复存储的至少一个有效存储器的互补状态信息。

公开(公告)号：US12212337B2

公开(公告)日：2025-01-28

申请号：US18128943

申请日：2023-03-30

Applicant: XILINX, INC. ,  Advanced Micro Devices, Inc.

Inventor： Kumar Rahul ,  John J. Wuu ,  Santosh Yachareni

IPC: H03M13/11 ,  H03M13/00

Abstract: An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.