-
公开(公告)号:US09916265B2
公开(公告)日:2018-03-13
申请号:US14569825
申请日:2014-12-15
Applicant: Advanced Micro Devices, Inc.
Inventor: Sergey Blagodurov , Gabriel H. Loh , Yasuko Eckert
CPC classification number: G06F13/1694 , G06F11/3414 , G06F12/023 , G06F13/161 , G06F2212/1044 , Y02D10/14
Abstract: A system includes a plurality of memory classes and a set of one or more processing units coupled to the plurality of memory classes. The system further includes a data migration controller to select a traffic rate as a maximum traffic rate for transferring data between the plurality of memory classes based on a net benefit metric associated with the traffic rate, and to enforce the maximum traffic rate for transferring data between the plurality of memory classes.
-
公开(公告)号:US20170344490A1
公开(公告)日:2017-11-30
申请号:US15167038
申请日:2016-05-27
Applicant: Advanced Micro Devices, Inc.
Inventor: Sergey Blagodurov , Andrew G. Kegel
IPC: G06F12/1009 , G06F3/06
Abstract: The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.
-
公开(公告)号:US20170228321A1
公开(公告)日:2017-08-10
申请号:US15040195
申请日:2016-02-10
Applicant: Advanced Micro Devices, Inc.
Inventor: Sergey Blagodurov , Gabriel H. Loh , John R. Slice
CPC classification number: G06F12/122 , G06F3/0604 , G06F3/0629 , G06F3/0653 , G06F3/0685 , G06F11/34 , G06F12/0897 , G06F12/126 , G06F2212/1016 , G06F2212/2515 , G06F2212/502
Abstract: The described embodiments include a computer system having a multi-level memory hierarchy with two or more levels of memory, each level being one of two or more types of memory. The computer system handles storing objects in the multi-level memory hierarchy. During operation, a system runtime in the computer system identifies an object to be stored in the multi-level memory hierarchy. The system runtime then determines, based on one or more attributes of the object, that the object is to be pinned in a level of the multi-level memory hierarchy. The system runtime then pins the object in the level of the multi-level memory hierarchy. In the described embodiments, the pinning includes hard pinning and soft pinning, which are each associated with corresponding retention policies for pinned objects.
-
公开(公告)号:US20160371082A1
公开(公告)日:2016-12-22
申请号:US14746601
申请日:2015-06-22
Applicant: Advanced Micro Devices, Inc.
Inventor: Dmitri Yudanov , Sergey Blagodurov , Arkaprava Basu , Sooraj Puthoor , Joseph L. Greathouse
IPC: G06F9/30
CPC classification number: G06F9/461 , G06F9/3013 , G06F9/3851
Abstract: A processing device includes a first memory that includes a context buffer. The processing device also includes a processor core to execute threads based on context information stored in registers of the processor core and a memory controller to selectively move a subset of the context information between the context buffer and the registers based on one or more latencies of the threads.
Abstract translation: 处理装置包括包括上下文缓冲器的第一存储器。 处理设备还包括处理器核心,用于基于存储在处理器核心的寄存器中的上下文信息来执行线程,以及存储器控制器,用于基于上下文缓冲器和寄存器的一个或多个延迟来选择性地移动上下文信息的子集 线程。
-
公开(公告)号:US12174742B2
公开(公告)日:2024-12-24
申请号:US16220462
申请日:2018-12-14
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Sergey Blagodurov , Thaleia Dimitra Doudali , Amin Farmahini Farahani
IPC: G06F12/08 , G06F3/044 , G06F12/0862 , G06F12/1009 , G06F12/127 , G06N3/045
Abstract: A computer processing system having a first memory with a first set of memory pages resident therein and a second memory coupled to the first memory. A resource tracker provides information to instances of a long short-term memory (LSTM) recurrent neural network (RNN). A predictor identifies memory pages from the first set of memory pages for prediction by the one or more LSTM RNN instances. The system groups the memory pages of the identified plurality of memory pages into a number of patterns based on a number of memory accesses per time. An LSTM RNN instance predicts a number of page accesses for each pattern. A second set of memory pages is selected for moving from the first memory to the second memory.
-
公开(公告)号:US11709745B2
公开(公告)日:2023-07-25
申请号:US17588779
申请日:2022-01-31
Applicant: Advanced Micro Devices, Inc.
Inventor: Sergey Blagodurov , Michael Ignatowski , Vilas Sridharan
CPC classification number: G06F11/2094 , G06F2201/82
Abstract: A method includes, in response to a memory error indication indicating an uncorrectable error in a faulted segment, associating in a remapping table the faulted segment with a patch segment in a patch memory region, and in response to receiving from a processor a memory access request directed to the faulted segment, servicing the memory access request from the patch segment by performing the requested memory access at the patch segment based on a patch segment address identifying the location of the patch segment. The patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.
-
公开(公告)号:US11663073B2
公开(公告)日:2023-05-30
申请号:US17118434
申请日:2020-12-10
Applicant: Advanced Micro Devices, Inc.
Inventor: SeyedMohammad SeyedzadehDelcheh , Sergey Blagodurov
CPC classification number: G06F11/10
Abstract: An apparatus and method for efficiently transmitting data are described. A transmitter sends data to a receiver. An encoder of the transmitter divides a received first block of data into multiple sub-blocks. The encoder selects a portion of each sub-block to compare to one another. A portion in a particular sub-block has a same offset and a same size as other portions of other sub-blocks. If the encoder determines the multiple portions match one another, the encoder sends, to the receiver, a second block of data corresponding to the first block of data. The second block of data has a same size as a size of the received first block of data, and the second block of data includes security data from one of multiple error correction schemes. Therefore, the second block of data provides security without increasing an amount of data to transmit.
-
公开(公告)号:US20220198261A1
公开(公告)日:2022-06-23
申请号:US17131546
申请日:2020-12-22
Applicant: Advanced Micro Devices, Inc.
Inventor: Sergey Blagodurov , Yasuko Eckert , John D. Wilkes
Abstract: A system and method for providing for adoption of solvers for solving at least one task is disclosed. The system and method include a controller, solvers capable of solving the at least one task, and at least one memory. The controller admits ones of the solvers into a competition for solving the at least one task, provides, via the at least one memory, an input of the task to the admitted solvers, provides, via the at least one memory, intermediate results of execution by the admitted solvers that are provided the input, receives a prediction of the next intermediate result from the admitted solvers predicting from at least one of the provided input and received intermediate results, and ranks the at least one of the admitted solvers for solving the task based on at least one of the next intermediate results, the provided input and received intermediate results.
-
公开(公告)号:US20220197506A1
公开(公告)日:2022-06-23
申请号:US17124872
申请日:2020-12-17
Applicant: Advanced Micro Devices, Inc.
Inventor: Sergey Blagodurov , Johnathan Alsop , SeyedMohammad SeyedzadehDelcheh
Abstract: Systems, apparatuses, and methods for determining data placement based on packet metadata are disclosed. A system includes a traffic analyzer that determines data placement across connected devices based on observed values of the metadata fields in actively exchanged packets across a plurality of protocol types. In one implementation, the protocol that is supported by the system is the compute express link (CXL) protocol. The traffic analyzer performs various actions in response to events observed in a packet stream that match items from a pre-configured list. Data movement is handled underneath the software applications by changing the virtual-to-physical address translation once the data movement is completed. After the data movement is finished, threads will pull in the new host physical address into their translation lookaside buffers (TLBs) via a page table walker or via an address translation service (ATS) request.
-
公开(公告)号:US20220188208A1
公开(公告)日:2022-06-16
申请号:US17118404
申请日:2020-12-10
Applicant: Advanced Micro Devices, Inc.
Inventor: Anthony Gutierrez , Yasuko Eckert , Sergey Blagodurov , Jagadish B. Kotra
IPC: G06F11/30 , G06F1/20 , G06F12/0815 , G11C11/406 , G06F9/48 , G06F9/30
Abstract: A method may include, in response to a change in an operating parameter of a processing unit, modifying a signal pathway to a processing circuit component of the processing unit, and communicating with the processing circuit component via the signal pathway.
-
-
-
-
-
-
-
-
-