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    Systems and methods for a low hold-time sequential input stage
    13.
    发明授权
    Systems and methods for a low hold-time sequential input stage 有权

    公开(公告)号：US09806696B1

    公开(公告)日：2017-10-31

    申请号：US14978165

    申请日：2015-12-22

    Applicant: Altera Corporation

    Inventor： Dana How ,  Herman Henry Schmit

    IPC: H03K3/00 ,  H03K3/037

    CPC classification number: H03K3/037 ,  H03K19/17744

    Abstract: Systems and methods for a low hold-time sequential input stage provide circuitry that includes a first latch element receiving a first input. The first latch element is connected to a first two-input multiplexer. The circuitry further includes a second latch element receiving a second input. The second latch element is connected to the first two-input multiplexer. The first input and the second input originate from different input cells of an input column that receive a same source signal.

    Self-stuffing multi-clock FIFO requiring no synchronizers
    14.
    发明授权
    Self-stuffing multi-clock FIFO requiring no synchronizers 有权

    公开(公告)号：US09703526B2

    公开(公告)日：2017-07-11

    申请号：US14656300

    申请日：2015-03-12

    Applicant: Altera Corporation

    Inventor： Dana How

    IPC: G06F5/06 ,  G11C19/28 ,  G06F5/08

    CPC classification number: G06F5/06 ,  G06F5/08 ,  G11C19/28 ,  G11C19/287

    Abstract: An asynchronous first in first out memory device eliminates the need for synchronizers. The device includes pipeline of data registers. The data registers include a first register to accept data writes of data and a last register data reads. Each register has an enable input to indicate a full condition allowing a read and an empty condition allowing a write. A bubble inserter circuit inserts a bubble in the first register to prevent a completely empty condition for all registers. Controllers are associated with each register to allow the bubble or written data to be passed from the first register to the last register. A near empty detect circuit is coupled to the registers to determine a nearly empty condition of the pipeline. An arbiter determines whether a data write proceeds or a bubble insertion proceeds for the first register when the plurality of registers is near empty.

    Programmable logic device with integrated network-on-chip
    16.
    发明授权
    Programmable logic device with integrated network-on-chip 有权
    具有集成片上芯片的可编程逻辑器件

    公开(公告)号：US09479456B2

    公开(公告)日：2016-10-25

    申请号：US14066425

    申请日：2013-10-29

    Applicant: Altera Corporation

    Inventor： Michael David Hutton ,  Herman Henry Schmit ,  Dana How

    IPC: H04L12/933 ,  G06F15/78

    CPC classification number: H04L49/109 ,  G06F15/7825 ,  H04L41/0893 ,  H04L41/12 ,  H04L47/805

    Abstract: Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.

    Abstract translation: 用于在集成电路上提供用于高速数据传输的片上网络（NoC）结构的系统和方法。 在某些方面，NoC结构包括具有与集成电路的本地组件的双向连接的硬IP接口的多个NoC站。 在某些方面，NoC站具有支持NoC站的硬IP接口的软IP接口。

    Level-sensitive two-phase single-wire latch controllers without contention
    17.
    发明授权
    Level-sensitive two-phase single-wire latch controllers without contention 有权
    电平敏感的两相单线锁存器控制器，无争议

    公开(公告)号：US09385717B1

    公开(公告)日：2016-07-05

    申请号：US14291487

    申请日：2014-05-30

    Applicant: Altera Corporation

    Inventor： Dana How

    IPC: H03K19/0175 ,  H03K19/094

    CPC classification number: H03K19/0175 ,  G06F9/3869 ,  H03K3/038 ,  H03K19/0966

    Abstract: Systems and methods are described for a contention-free single-wire latch controller that includes first and second bidirectional signal pins (e.g., the L and R pins in the FIGS), a latch enable output pin (or signal), E, and a decision element (such as a NAND or a NOR gate). A first driving transistor may be coupled between the first bidirectional signal pin and a power rail. A second driving transistor may be coupled between the second bidirectional signal pin and the power rail. A first half-latch may be coupled to the first bidirectional signal pin. A second half-latch may be coupled to the second bidirectional signal pin.

    Abstract translation: 描述了一种无竞争的单线锁存控制器的系统和方法，该控制器包括第一和第二双向信号引脚（例如，图中的L和R引脚），锁存使能输出引脚（或信号）E和 决定元件（如NAND或NOR门）。 第一驱动晶体管可以耦合在第一双向信号引脚和电源轨之间。 第二驱动晶体管可以耦合在第二双向信号引脚和电源轨之间。 第一半锁存器可以耦合到第一双向信号引脚。 第二半锁存器可以耦合到第二双向信号引脚。

    System Reset Controller Replacing Individual Asynchronous Resets
    18.
    发明申请
    System Reset Controller Replacing Individual Asynchronous Resets 有权
    系统复位控制器更换单个异步复位

    公开(公告)号：US20150295579A1

    公开(公告)日：2015-10-15

    申请号：US14249292

    申请日：2014-04-09

    Applicant: Altera Corporation

    Inventor： Dana How

    IPC: H03K19/177 ,  G06F17/50

    CPC classification number: H03K19/1774 ,  G06F17/5054

    Abstract: An integrated circuit device comprises a system reset controller. The system reset controller includes a clock signal input, a reset signal input, a clock signal output, and a reset signal output. The system reset controller is arranged to receive distributed clock and reset signal inputs and output modified clock and reset signal outputs such that asynchronous reset inputs in downstream system components can be replaced by logic elements not requiring asynchronous reset inputs with no change in externally-visible behavior except the length of reset sequences as measured by clock pulses.

    Abstract translation: 集成电路装置包括系统复位控制器。 系统复位控制器包括时钟信号输入，复位信号输入，时钟信号输出和复位信号输出。 系统复位控制器被布置为接收分布式时钟和复位信号输入并输出修改的时钟和复位信号输出，使得下游系统组件中的异步复位输入可以由不需要异步复位输入的逻辑元件代替，而外部可见行为没有变化 除了由时钟脉冲测量的复位序列的长度之外。

    PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP
    19.
    发明申请
    PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP 有权
    具有集成网络芯片的可编程逻辑器件

    公开(公告)号：US20140126572A1

    公开(公告)日：2014-05-08

    申请号：US14066425

    申请日：2013-10-29

    Applicant: Altera Corporation

    Inventor： Michael David Hutton ,  Herman Henry Schmit ,  Dana How

    IPC: H04L12/931

    CPC classification number: H04L49/109 ,  G06F15/7825 ,  H04L41/0893 ,  H04L41/12 ,  H04L47/805

    Abstract: Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.

    Abstract translation: 用于在集成电路上提供用于高速数据传输的片上网络（NoC）结构的系统和方法。 在某些方面，NoC结构包括具有与集成电路的本地组件的双向连接的硬IP接口的多个NoC站。 在某些方面，NoC站具有支持NoC站的硬IP接口的软IP接口。

    Programmable integrated circuits with in-operation reconfiguration capability
    20.
    发明授权
    Programmable integrated circuits with in-operation reconfiguration capability 有权

    公开(公告)号：US10591544B2

    公开(公告)日：2020-03-17

    申请号：US16043035

    申请日：2018-07-23

    Applicant: Altera Corporation

    Inventor： Dana How ,  Dinesh Patil ,  Arifur Rahman ,  Jeffrey Erik Schulz

    IPC: G06F11/20 ,  G06F11/16 ,  G01R31/3185 ,  G06F11/18 ,  G06F11/00 ,  G01R31/28 ,  H01L25/065

    Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.

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