公开(公告)号：US10523224B2

公开(公告)日：2019-12-31

申请号：US16414451

申请日：2019-05-16

Applicant: Altera Corporation

Inventor： David Mendel ,  Carl Ebeling ,  Dana How ,  Mahesh Iyer

IPC: H03L7/23 ,  H03L7/089 ,  H03L7/099 ,  H03L7/093

Abstract: An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

公开(公告)号：US10333535B1

公开(公告)日：2019-06-25

申请号：US15278409

申请日：2016-09-28

Applicant: Altera Corporation

Inventor： David Mendel ,  Carl Ebeling ,  Dana How ,  Mahesh Iyer

IPC: H03L7/23 ,  H03L7/099 ,  H03L7/089 ,  H03L7/093

Abstract: An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

公开(公告)号：US09606573B1

公开(公告)日：2017-03-28

申请号：US14752393

申请日：2015-06-26

Applicant: Altera Corporation

Inventor： Carl Ebeling ,  Dana How ,  Herman Henry Schmit ,  Vadim Gutnik ,  Ramanand Venkata

IPC: H03K3/00 ,  G06F1/08

CPC classification number: G06F1/08 ,  G06F1/10

Abstract: Circuitry accepts an input signal and distributes the input signal to a plurality of locations within the circuitry. The circuitry includes a first circuit element and a second circuit element. The circuitry further includes a first plurality of wire segments that are substantially aligned to form a first bundle, and include a first wire segment. The circuitry further includes a second plurality of wire segments that are substantially aligned to form a second bundle, and have a second wire segment. An intersection element of the first bundle and the second bundle includes a first interconnecting wire segment that connects the first wire segment and the second wire segment, and the input signal is routed from the first wire segment to the second wire segment via the first interconnecting wire segment. The input signal is further transmitted to the second element from the second wire segment.

公开(公告)号：US10141936B2

公开(公告)日：2018-11-27

申请号：US15630436

申请日：2017-06-22

Applicant: Altera Corporation

Inventor： David Lewis ,  Herman Henry Schmit ,  Carl Ebeling

IPC: H03K19/0175 ,  H03K19/173 ,  H03K19/0185

Abstract: An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to store one or two signals per clock period. Operating the pipeline interconnects in double data rate mode may provide a trade-off between reducing the number of physical wires that are required to implement a design at a constant bandwidth or increasing the bandwidth while keeping the number of physical wires constant.

公开(公告)号：US09558796B2

公开(公告)日：2017-01-31

申请号：US14526007

申请日：2014-10-28

Applicant: Altera Corporation

Inventor： Carl Ebeling ,  Pohrong Rita Chu

IPC: G11C7/10 ,  H03K19/177

CPC classification number: G11C7/1039 ,  G11C7/1033 ,  H03K19/1776 ,  H03K19/17764

Abstract: Enhanced memory circuits are described that maintain coherency between concurrent memory reads and writes in a pipelined memory architecture. The described memory circuits can maintain data coherency regardless of the amount of pipelining applied to the memory inputs and/or outputs. Moreover, these memory circuits may be implemented as dedicated hard circuits in a field programmable gate array (FPGA) or other programmable logic device (PLD), and can be supplemented with user-configurable logic to achieve coherency in a variety of applications.

Abstract translation: 描述了在流水线存储器架构中保持并发存储器读取和写入之间的一致性的增强型存储器电路。 所描述的存储器电路可以保持数据一致性，而不管施加到存储器输入和/或输出的流水线量。 此外，这些存储器电路可以被实现为现场可编程门阵列（FPGA）或其他可编程逻辑器件（PLD）中的专用硬电路，并且可以用用户可配置逻辑来补充以在各种应用中实现一致性。

公开(公告)号：US09501092B1

公开(公告)日：2016-11-22

申请号：US14974506

申请日：2015-12-18

Applicant: Altera Corporation

Inventor： Dana How ,  Carl Ebeling ,  Audrey Catherine Kertesz

IPC: H03L7/06 ,  G06F1/12

CPC classification number: H04L7/02 ,  G06F1/12 ,  H04L7/0054

Abstract: Systems and methods for phase detection are disclosed. A collapsible three-stage pipeline includes a first register in a first stage having a first clock signal having first clock edges, a second register in a second stage that receives a first signal from the first stage, and having a second clock signal having second clock edges, and a third register in a third stage that receives a second signal from the second stage, and having a third clock signal having third clock edges, wherein each second clock edge has a corresponding first clock edge and a corresponding third clock edge. The circuitry may further include a two-stage pipeline including fourth and fifth stages, a counter that provides an input signal into the collapsible three-stage pipeline and the two-stage pipeline, and a comparator that compares a first output of the collapsible three-stage pipeline and a second output of the two-stage pipeline.

Abstract translation: 公开了用于相位检测的系统和方法。 可折叠三级流水线包括第一级中的第一寄存器，其具有具有第一时钟沿的第一时钟信号，第二级中的第二寄存器，其接收来自第一级的第一信号，并具有第二时钟信号，该第二时钟信号具有第二时钟 边缘和第三寄存器，其接收来自第二级的第二信号，并具有具有第三时钟沿的第三时钟信号，其中每个第二时钟沿具有对应的第一时钟沿和对应的第三时钟沿。 该电路还可以包括一个包括第四和第五级的两级流水线，一个向可折叠的三级流水线和两级流水线提供输入信号的计数器，以及比较器， 阶段管道和二级管道的第二输出。

公开(公告)号：US20170288671A1

公开(公告)日：2017-10-05

申请号：US15630436

申请日：2017-06-22

Applicant: Altera Corporation

Inventor： David Lewis ,  Herman Henry Schmit ,  Carl Ebeling

IPC: H03K19/0175 ,  H03K19/173

CPC classification number: H03K19/017581 ,  H03K19/017509 ,  H03K19/018521 ,  H03K19/1737

Abstract: An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to store one or two signals per clock period. Operating the pipeline interconnects in double data rate mode may provide a trade-off between reducing the number of physical wires that are required to implement a design at a constant bandwidth or increasing the bandwidth while keeping the number of physical wires constant.

公开(公告)号：US20160118089A1

公开(公告)日：2016-04-28

申请号：US14526007

申请日：2014-10-28

Applicant: Altera Corporation

Inventor： Carl Ebeling ,  Pohrong Rita Chu

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1033 ,  H03K19/1776 ,  H03K19/17764

Abstract: Enhanced memory circuits are described that maintain coherency between concurrent memory reads and writes in a pipelined memory architecture. The described memory circuits can maintain data coherency regardless of the amount of pipelining applied to the memory inputs and/or outputs. Moreover, these memory circuits may be implemented as dedicated hard circuits in a field programmable gate array (FPGA) or other programmable logic device (PLD), and can be supplemented with user-configurable logic to achieve coherency in a variety of applications.

Abstract translation: 描述了在流水线存储器架构中保持并发存储器读取和写入之间的一致性的增强型存储器电路。 所描述的存储器电路可以保持数据一致性，而不管施加到存储器输入和/或输出的流水线量。 此外，这些存储器电路可以被实现为现场可编程门阵列（FPGA）或其他可编程逻辑器件（PLD）中的专用硬电路，并且可以用用户可配置逻辑来补充以在各种应用中实现一致性。

公开(公告)号：US09960903B1

公开(公告)日：2018-05-01

申请号：US15332773

申请日：2016-10-24

Applicant: Altera Corporation

Inventor： Dana How ,  Carl Ebeling ,  Audrey Catherine Kertesz

IPC: H04L25/38 ,  H04L7/02 ,  H04L7/00

CPC classification number: H04L7/02 ,  G06F1/12 ,  H04L7/0054

Abstract: Systems and methods for phase detection are disclosed. Phase alignment between first and second clock signals is detected using a comparison of outputs from a collapsible pipeline and a non-collapsible pipeline.

公开(公告)号：US09824024B1

公开(公告)日：2017-11-21

申请号：US14530576

申请日：2014-10-31

Applicant: Altera Corporation

Inventor： Carl Ebeling ,  Jeffrey Christopher Chromczak ,  David Lewis

IPC: G06F12/00 ,  G06F12/1072 ,  G06F12/1009 ,  G06F13/28 ,  G06F12/0875

CPC classification number: G06F13/287 ,  H03K19/1776

Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, an arithmetic circuit, and a control circuit. The control circuit may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement first-in first-out modules, shift registers, or delay-line modules in addition to implementing memory modules with random access.