公开(公告)号：US20180041328A1

公开(公告)日：2018-02-08

申请号：US15226037

申请日：2016-08-02

Applicant: Altera Corporation

Inventor： Dinesh Patil ,  Kok Hong Chan ,  Wai Tat Wong ,  Chuan Thim Khor

IPC: H04L7/00 ,  H03K19/177 ,  H04L12/863 ,  H03L7/08

CPC classification number: H03K19/1776 ,  G06F1/04 ,  G06F1/12 ,  G11C7/222 ,  H03K19/17728 ,  H03L7/0805 ,  H03L7/0814 ,  H04L47/56

Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.

公开(公告)号：US10439615B2

公开(公告)日：2019-10-08

申请号：US16246629

申请日：2019-01-14

Applicant: Altera Corporation

Inventor： Dinesh Patil ,  Kok Hong Chan ,  Wai Tat Wong ,  Chuan Thim Khor

IPC: H03K19/177 ,  G06F1/04 ,  H03L7/08 ,  H03L7/081 ,  H04L12/875 ,  G06F1/12 ,  G11C7/22

Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.

公开(公告)号：US20190018063A1

公开(公告)日：2019-01-17

申请号：US16043035

申请日：2018-07-23

Applicant: Altera Corporation

Inventor： Dana How ,  Dinesh Patil ,  Arifur Rahman ,  Jeffrey Erik Schulz

IPC: G01R31/3185 ,  G06F11/00 ,  G06F11/20 ,  G06F11/18 ,  G01R31/28 ,  H01L25/065 ,  G06F11/16

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

公开(公告)号：US10031182B2

公开(公告)日：2018-07-24

申请号：US14737246

申请日：2015-06-11

Applicant: Altera Corporation

Inventor： Dana How ,  Dinesh Patil ,  Arifur Rahman ,  Jeffrey Erik Schulz

IPC: G06F13/00 ,  G06F13/20 ,  G06F3/00 ,  G01R31/3185 ,  G01R31/28 ,  H01L25/065 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F11/00

Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.

公开(公告)号：US10591544B2

公开(公告)日：2020-03-17

申请号：US16043035

申请日：2018-07-23

Applicant: Altera Corporation

Inventor： Dana How ,  Dinesh Patil ,  Arifur Rahman ,  Jeffrey Erik Schulz

IPC: G06F11/20 ,  G06F11/16 ,  G01R31/3185 ,  G06F11/18 ,  G06F11/00 ,  G01R31/28 ,  H01L25/065

Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.

公开(公告)号：US10218360B2

公开(公告)日：2019-02-26

申请号：US15226037

申请日：2016-08-02

Applicant: Altera Corporation

Inventor： Dinesh Patil ,  Kok Hong Chan ,  Wai Tat Wong ,  Chuan Thim Khor

IPC: H03K19/177 ,  G06F1/04 ,  H03L7/08 ,  H03L7/081 ,  H04L12/875 ,  G06F1/12 ,  G11C7/22

Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.

公开(公告)号：US10082541B2

公开(公告)日：2018-09-25

申请号：US14737246

申请日：2015-06-11

Applicant: Altera Corporation

Inventor： Dana How ,  Dinesh Patil ,  Arifur Rahman ,  Jeffrey Erik Schulz

IPC: G06F13/00 ,  G06F13/20 ,  G06F3/00 ,  G01R31/3185 ,  G01R31/28 ,  H01L25/065 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F11/00

Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.

公开(公告)号：US09595495B1

公开(公告)日：2017-03-14

申请号：US14867463

申请日：2015-09-28

Applicant: ALTERA CORPORATION

Inventor： Dinesh Patil

IPC: H01L23/538 ,  H03M1/66 ,  H03M1/12

CPC classification number: H01L23/5381 ,  H01L23/5385 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: One embodiment relates to an apparatus for data communication between at least two in-package semiconductor dies. On the first semiconductor die in a package, a digital-to-analog converter (DAC) converts a plurality of binary signals to an analog signal. The analog signal is transmitted through a silicon bridge to a second semiconductor die. Another embodiment relates to a method of data communication between at least two in-package semiconductor dies. A plurality of binary signals is converted to an analog signal by a digital-to-analog converter on a first semiconductor die. The analog signal is transmitted through a silicon bridge to a second semiconductor die. Other embodiments, aspects and features are also disclosed.

Abstract translation: 一个实施例涉及用于至少两个封装内半导体管芯之间的数据通信的装置。 在封装中的第一半导体管芯上，数模转换器（DAC）将多个二进制信号转换为模拟信号。 模拟信号通过硅桥传输到第二半导体管芯。 另一实施例涉及至少两个封装内半导体管芯之间的数据通信方法。 多个二进制信号通过第一半导体管芯上的数模转换器转换为模拟信号。 模拟信号通过硅桥传输到第二半导体管芯。 还公开了其它实施例，方面和特征。

公开(公告)号：US20160363626A1

公开(公告)日：2016-12-15

申请号：US14737246

申请日：2015-06-11

Applicant: Altera Corporation

Inventor： Dana How ,  Dinesh Patil ,  Arifur Rahman ,  Jeffrey Erik Schulz

IPC: G01R31/3185 ,  G01R31/28 ,  H01L25/065

CPC classification number: G01R31/318597 ,  G01R31/2896 ,  G06F11/00 ,  G06F11/1625 ,  G06F11/186 ,  G06F11/2007 ,  H01L25/0652 ,  H01L2225/06527

Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.

Abstract translation: 提供了具有多个集成电路管芯的集成电路封装。 多芯片封装可以包括通过晶片间封装互连耦合到一个或多个从裸片的主裸片。 可以实施混合（即，主动和被动）互连冗余方案以帮助修复潜在的故障互连以提高组装产量。 携带正常用户信号的互连可以使用主动冗余方案通过在必要时选择性地切换到使用备用驱动器块来修复。 另一方面，可以使用无源冗余方案来支持携带上电复位信号，初始化信号和用于同步主器件和从器件之间的操作的其他关键控制信号的互连，通过使用两个或更多个复制线来为每个 关键信号。

公开(公告)号：US09520324B1

公开(公告)日：2016-12-13

申请号：US14588098

申请日：2014-12-31

Applicant: Altera Corporation

Inventor： Dinesh Patil ,  Minqing Cai

IPC: H01L29/00 ,  H01L21/768 ,  H01L27/06 ,  H01L23/50

CPC classification number: H01L23/50 ,  H01L23/647 ,  H01L25/0655

Abstract: An integrated circuit system, and a method of manufacture thereof, includes an integrated circuit package connected to a package interconnect connectible to an external resistor, wherein the integrated circuit package includes a master integrated circuit and a slave integrated circuit, the master integrated circuit is connectible to the external resistor and the slave integrated circuit, the master integrated circuit includes a master constant current and a slave constant current, the master constant current flows through the external resistor, and the slave constant current is based on the master constant current.

Abstract translation: 集成电路系统及其制造方法包括连接到可连接到外部电阻器的封装布线的集成电路封装，其中集成电路封装包括主集成电路和从集成电路，主集成电路可连接 对于外部电阻和从集成电路，主集成电路包括主恒定电流和从恒定电流，主恒定电流通过外部电阻流动，从动恒定电流基于主恒定电流。