公开(公告)号：US09362107B2

公开(公告)日：2016-06-07

申请号：US14502492

申请日：2014-09-30

Applicant: Applied Materials, Inc.

Inventor： Kiran V. Thadani ,  Abhijit Basu Mallick ,  Sanjay Kamath

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L21/02126 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/76224 ,  H01L21/76837

Abstract: Methods are described for forming a flowable low-k dielectric film on a patterned substrate. The film may be a silicon-carbon-oxygen (Si—C—O) layer in which the silicon and carbon constituents come from a silicon and carbon containing precursor while the oxygen may come from an oxygen-containing precursor activated in a remote plasma region. Shortly after deposition, the silicon-carbon-oxygen layer is treated by exposure to a hydrogen-and-nitrogen-containing precursor such as ammonia prior to curing. The treatment may remove residual moisture from the silicon-carbon-oxygen layer and may make the lattice more resilient during curing and subsequent processing. The treatment may reduce shrinkage of the silicon-carbon-oxygen layer during subsequent processing.

Abstract translation: 描述了在图案化衬底上形成可流动的低k电介质膜的方法。 该膜可以是硅 - 碳 - 氧（Si-C-O）层，其中硅和碳成分来自含硅和碳的前体，而氧可以来自在远程等离子体区域中激活的含氧前体 。 沉积后不久，在固化之前通过暴露于含氢和氮的前体如氨来处理硅 - 碳 - 氧层。 该处理可以从硅 - 碳 - 氧层去除残留的水分，并且可以使晶格在固化和随后的加工过程中更有弹性。 该处理可以在随后的处理期间减小硅 - 碳 - 氧层的收缩。

公开(公告)号：US12040210B2

公开(公告)日：2024-07-16

申请号：US17073671

申请日：2020-10-19

Applicant: Applied Materials, Inc.

Inventor： Jian Li ,  Dmitry A. Dzilno ,  Juan Carlos Rocha-Alvarez ,  Paul L. Brillhart ,  Akshay Gunaji ,  Mayur Govind Kulkarni ,  Sandeep Bindgi ,  Sanjay Kamath ,  Kwangduk Douglas Lee ,  Zongbin Wang ,  Yubin Zhang ,  Yong Xiang Lim

IPC: H01L21/683 ,  C23C16/458 ,  C23C16/50 ,  H01J37/32 ,  H01L21/687

CPC classification number: H01L21/6833 ,  C23C16/4586 ,  C23C16/50 ,  H01J37/32715 ,  H01L21/68742 ,  H01J2237/2007 ,  H01J2237/3321

Abstract: Exemplary semiconductor processing systems include a processing chamber, a power supply, and a chuck disposed at least partially within the processing chamber. The chuck includes a chuck body defining a vacuum port. The chuck also includes first and second coplanar electrodes embedded in the chuck body and connected to the power supply. In some examples, coplanar electrodes include concentric electrodes defining a concentric gap in between. Exemplary semiconductor processing methods may include activating the power supply for the electrostatic chuck to secure a semiconductor substrate on the body of the chuck and/or activating the vacuum port defined by the body of the electrostatic chuck. Some processing can be carried out at increased pressure, while other processing can be carried out at reduced pressure with increased chucking voltage.

公开(公告)号：US11817320B2

公开(公告)日：2023-11-14

申请号：US16554834

申请日：2019-08-29

Applicant: Applied Materials, Inc.

Inventor： Susmit Singha Roy ,  Kelvin Chan ,  Hien Minh Le ,  Sanjay Kamath ,  Abhijit Basu Mallick ,  Srinivas Gandikota ,  Karthik Janakiraman

IPC: C23C16/50 ,  H01L21/285 ,  H01L21/02 ,  C23C16/06 ,  C23C16/02 ,  C23C16/40 ,  C23C16/505 ,  C23C28/00 ,  H01L21/3205 ,  H01L21/768 ,  H10B43/27

CPC classification number: H01L21/28506 ,  C23C16/0272 ,  C23C16/06 ,  C23C16/402 ,  C23C16/505 ,  C23C28/322 ,  C23C28/34 ,  C23C28/345 ,  C23C28/42 ,  H01L21/0245 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/02458 ,  H01L21/02491 ,  H01L21/02697 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32051 ,  H01L21/76876 ,  H10B43/27

Abstract: Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.

公开(公告)号：US11430654B2

公开(公告)日：2022-08-30

申请号：US16698500

申请日：2019-11-27

Applicant: Applied Materials, Inc.

Inventor： Madhu Santosh Kumar Mutyala ,  Sanjay Kamath ,  Deenesh Padhi

IPC: H01L21/31 ,  H01L21/02 ,  H01J37/32 ,  C23C16/458 ,  C23C16/50

Abstract: Exemplary deposition methods may include forming a plasma of an oxygen-containing precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include, while maintaining the plasma of the oxygen-containing precursor, flowing a silicon-containing precursor into the processing region of the semiconductor processing chamber at a first flow rate. The methods may include ramping the first flow rate of the silicon-containing precursor over a period of time to a second flow rate greater than the first flow rate. The methods may include depositing a silicon-containing material on the semiconductor substrate.

公开(公告)号：US20220122811A1

公开(公告)日：2022-04-21

申请号：US17072673

申请日：2020-10-16

Applicant: Applied Materials, Inc.

Inventor： Madhu Santosh Kumar Mutyala ,  Sanjay Kamath ,  Deenesh Padhi ,  Mayur Govind Kulkarni ,  Arun Thottappayil

IPC: H01J37/32 ,  H01L21/02 ,  C23C16/40 ,  C23C16/50

Abstract: Exemplary deposition methods may include forming a plasma of an oxygen-containing precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include, while maintaining the plasma of the oxygen-containing precursor, flowing a silicon-containing precursor through a faceplate into the processing region of the semiconductor processing chamber. The faceplate may have an impedance of at least 5.75 deciohm. The methods may include depositing a silicon-containing material on the semiconductor substrate.

公开(公告)号：US11157661B2

公开(公告)日：2021-10-26

申请号：US16716274

申请日：2019-12-16

Applicant: Applied Materials, Inc.

Inventor： Vinayak Veer Vats ,  Sidharth Bhatia ,  Garrett Ho-Yee Sin ,  Pramod Nambiar ,  Hang Yu ,  Sanjay Kamath ,  Deenesh Padhi ,  Heng-Cheng Pai

IPC: G06F30/12 ,  G06F16/904 ,  G06F16/903 ,  G06F119/18

Abstract: A process development visualization tool generates a first visualization of a parameter associated with a manufacturing process, and provides a GUI control element associated with a process variable of the manufacturing process, wherein the GUI control element has a first setting associated with a first value for the process variable. The process development tool receives a user input to adjust the GUI control element from the first setting to a second setting, determines a second value for the process variable based on the second setting, and determines a second set of values for the parameter that are associated with the second value for the process variable. The process development tool then generates a second visualization of the parameter, wherein the second visualization represents the second set of values for the parameter that are associated with the second value for the process variable.

公开(公告)号：US20210242016A1

公开(公告)日：2021-08-05

申请号：US16782933

申请日：2020-02-05

Applicant: Applied Materials, Inc.

Inventor： Madhu Santosh Kumar Mutyala ,  Sanjay Kamath ,  Deenesh Padhi

IPC: H01L21/02 ,  H01J37/32 ,  C23C16/40 ,  C23C16/50

Abstract: Exemplary deposition methods may include forming a plasma of a silicon-containing precursor and at least one additional precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include depositing material on the semiconductor substrate to a target thickness. The methods may include halting delivery of the silicon-containing precursor while maintaining the plasma with the one or more precursors. The methods may include purging the processing region of the semiconductor processing chamber.