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公开(公告)号：US20170010892A1
公开(公告)日：2017-01-12
申请号：US14794835
申请日：2015-07-09
Applicant: Centipede Semi Ltd.
Inventor： Noam Mizrahi , Jonathan Friedmann
CPC classification number: G06F9/30043 , G06F9/3824 , G06F9/3826 , G06F9/3832 , G06F9/3834
Abstract: A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. A relationship between the memory addresses accessed by two or more of the memory-access instructions is identified, based on respective formats of the memory addresses specified in the symbolic expressions. An outcome of at least one of the memory-access instructions is assigned to be served from an internal memory in the processor, based on the identified relationship.
Abstract translation: 一种方法在处理器中包括包括存储器访问指令的处理程序代码，其中至少一些存储器访问指令包括根据一个或多个寄存器名称指定外部存储器中的存储器地址的符号表达式。 基于符号表达式中指定的存储器地址的相应格式，识别由两个或多个存储器访问指令访问的存储器地址之间的关系。 基于所识别的关系，从处理器中的内部存储器分配至少一个存储器访问指令的结果。
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12.发明申请RUN-TIME PARALLELIZATION OF CODE EXECUTION BASED ON AN APPROXIMATE REGISTER-ACCESS SPECIFICATION 有权基于近似寄存器访问规范的代码执行的运行时间并行公开(公告)号：US20160306633A1
公开(公告)日：2016-10-20
申请号：US14690424
申请日：2015-04-19
Applicant: Centipede Semi Ltd.
Inventor： Noam Mizrahi , Alberto Mandler , Shay Koren , Jonathan Friedmann
CPC classification number: G06F9/3861 , G06F9/3808 , G06F9/382 , G06F9/3832 , G06F9/3838 , G06F9/3851 , G06F9/3857 , G06F9/3875 , G06F9/455 , G06F9/46 , G06F12/0833
Abstract: A method includes, in a processor that processes instructions of program code, processing a first segment of the instructions. One or more destination registers are identified in the first segment using an approximate specification of register access by the instructions. Respective values of the destination registers are made available to a second segment of the instructions only upon verifying that the values are valid for readout by the second segment in accordance with the approximate specification. The second segment is processed at least partially in parallel with processing of the first segment, using the values made available from the first segment.
Abstract translation: 一种方法包括在处理程序代码指令的处理器中处理指令的第一段。 使用指令的寄存器访问的近似规范，在第一段中标识一个或多个目的地寄存器。 目的地寄存器的相应值仅在验证该值对于根据近似规范由第二段读出有效时才可用于指令的第二段。 使用从第一段获得的值，至少部分地与第一段的处理并行处理第二段。
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13.发明授权Run-time code parallelization with approximate monitoring of instruction sequences 有权运行时代码并行化与指令序列的近似监视公开(公告)号：US09208066B1
公开(公告)日：2015-12-08
申请号：US14637418
申请日：2015-03-04
Applicant: Centipede Semi Ltd.
Inventor： Noam Mizrahi , Alberto Mandler , Shay Koren , Jonathan Friedmann
CPC classification number: G06F11/3024 , G06F8/452 , G06F8/456 , G06F9/48 , G06F11/3404
Abstract: A method includes, in a processor that executes instructions of program code, identifying a region of the code containing one or more segments of the instructions that are at least partially repetitive. The instructions in the region are monitored, and an approximate specification of register access by the monitored instructions is constructed for the region. Execution of the segments in the region is parallelized using the specification.
Abstract translation: 一种方法包括在执行程序代码的指令的处理器中，识别包含至少部分重复的指令的一个或多个段的代码的区域。 监视该区域中的指令，并为该区域构建受监视指令的寄存器访问的近似规范。 使用规范并行执行区域中的段。
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公开(公告)号：US10296346B2
公开(公告)日：2019-05-21
申请号：US14673884
申请日：2015-03-31
Applicant: CENTIPEDE SEMI LTD.
Inventor： Noam Mizrahi , Alberto Mandler , Shay Koren , Jonathan Friedmann
Abstract: A method which includes, in a processor that processes instructions of program code, processing one or more of the instructions in a first segment of the instructions by a first hardware thread. Upon detecting that an instruction defined as a parallelization point has been fetched for the first thread, a second hardware thread is invoked to process at least one of the instructions in a second segment of the instructions, at least partially in parallel with processing of the instructions of the first segment by the first hardware thread, in accordance with a specification of register access that is indicative of data dependencies between the first and second segments.
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公开(公告)号：US10185561B2
公开(公告)日：2019-01-22
申请号：US14794835
申请日：2015-07-09
Applicant: Centipede Semi Ltd.
Inventor： Noam Mizrahi , Jonathan Friedmann
Abstract: A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. A relationship between the memory addresses accessed by two or more of the memory-access instructions is identified, based on respective formats of the memory addresses specified in the symbolic expressions. An outcome of at least one of the memory-access instructions is assigned to be served from an internal memory in the processor, based on the identified relationship.
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Patent Agency Ranking
公开(公告)号：US10180841B2
公开(公告)日：2019-01-15
申请号：US15007299
申请日：2016-01-27
Applicant: Centipede Semi Ltd.
Inventor： Noam Mizrahi , Alberto Mandler , Shay Koren , Jonathan Friedmann
Abstract: A processor includes a processing pipeline including multiple hardware threads and configured to execute software code instructions that are stored in a memory, along with multiple registers, configured to be read and written to by the processing pipeline during execution of the instructions. A monitoring unit monitors the instructions in the processing pipeline and records respective monitoring tables indicating the registers accessed in processing the instructions in different sequences of the instructions, and parallelizes among the hardware threads of the processor, using the respective monitoring tables, execution of repetitions of at least first sequences of the instructions. The monitoring unit is configured to evaluate a termination criterion based on the monitored instructions while monitoring the processing and recording the respective monitoring tables, and upon meeting the termination criterion, to terminate the monitoring before completion of the recording of the respective monitoring tables for at least second sequences of the instructions.
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公开(公告)号：US20180129498A1
公开(公告)日：2018-05-10
申请号：US15690560
申请日：2017-08-30
Applicant: Centipede Semi Ltd.
Inventor： Nadav LEVISON , Noam Mizrahi , Jonathan Friedmann
CPC classification number: G06F9/30069 , G06F9/30007 , G06F9/30021 , G06F9/30043 , G06F9/30145 , G06F9/3017 , G06F9/30181 , G06F9/3802 , G06F9/3812 , G06F9/3861
Abstract: Method(s) for up/down fusion and/or pseudo-fusion of micro-operations are performed in a hardware processor configured to execute program code. A mergeable pair of micro-operations is identified in a sequence of micro-operations of the program code. The pair of micro-operations includes a first micro-operation for performing a first function and a non-consecutive second micro-operation for performing a second function. The first micro-operation precedes the second micro-operation in the sequence of micro-operations being processed. The first micro-operation is merged into the second micro-operation to create a third micro-operation which performs both the first function and the second function. In up/down fusion the third micro-operation is dispatched instead of the first micro-operation or instead of the second micro-operation, based on whether fuse-up or fuse-down is performed. In pseudo-fusion the first micro-operation is retained in the sequence of micro-operations and the second micro-operation is replaced with the third micro-operation.
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公开(公告)号：US20170337062A1
公开(公告)日：2017-11-23
申请号：US15393291
申请日：2016-12-29
Applicant: Centipede Semi Ltd.
Inventor： Jonathan Friedmann , Shay Koren , Noam Mizrahi , Alberto Mandler
CPC classification number: G06F9/3814 , G06F9/3005 , G06F9/3804 , G06F9/3808 , G06F9/3842 , G06F9/3855 , G06F9/3861 , G06F9/3867
Abstract: A processor includes a pipeline and control circuitry. The pipeline is configured to process instructions of program code and includes one or more fetch units. The control circuitry is configured to predict at run-time one or more future flow-control traces to be traversed in the program code, to define, based on the predicted flow-control traces, two or more regions of the program code from which instructions are to be fetched, wherein the number of regions is greater than the number of fetch units, and to instruct the pipeline to fetch instructions alternately from the two or more regions of the program code using the one or more fetch units, and to process the fetched instructions.
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19.发明授权Processor with efficient processing of recurring load instructions from nearby memory addresses 有权处理器可以从附近的存储器地址处理循环加载指令公开(公告)号：US09575897B2
公开(公告)日：2017-02-21
申请号：US14794837
申请日：2015-07-09
Applicant: Centipede Semi Ltd.
Inventor： Noam Mizrahi , Jonathan Friedmann
CPC classification number: G06F12/0875 , G06F8/4442 , G06F9/30181 , G06F9/30196 , G06F9/345 , G06F9/35 , G06F9/383 , G06F9/3832 , G06F9/3834 , G06F9/384 , G06F9/3851 , G06F9/3867 , G06F12/0862 , G06F2212/452 , G06F2212/6026
Abstract: A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. Based on respective formats of the memory addresses specified in the symbolic expressions, a sequence of load instructions that access a predictable pattern of memory addresses in the external memory is identified. At least one cache line that includes a plurality of data values is retrieved from the external memory. Based on the predictable pattern, two or more of the data values that are requested by respective load instructions in the sequence are saved from the cache line to the internal memory. The saved data values are assigned to be served from the internal memory to one or more instructions that depend on the respective load instructions.
Abstract translation: 一种方法在处理器中包括包括存储器访问指令的处理程序代码，其中至少一些存储器访问指令包括根据一个或多个寄存器名称指定外部存储器中的存储器地址的符号表达式。 基于在符号表达式中指定的存储器地址的相应格式，识别访问外部存储器中的可预测的存储器地址模式的加载指令序列。 从外部存储器检索包括多个数据值的至少一个高速缓存行。 基于可预测的模式，将序列中的各个加载指令请求的两个或多个数据值从高速缓存行保存到内部存储器。 保存的数据值被分配为从内部存储器提供到依赖于相应负载指令的一个或多个指令。
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公开(公告)号：US20170010973A1
公开(公告)日：2017-01-12
申请号：US14794853
申请日：2015-07-09
Applicant: Centipede Semi Ltd.
Inventor： Noam Mizrahi , Jonathan Friedmann
CPC classification number: G06F12/0875 , G06F9/30043 , G06F9/3016 , G06F9/34 , G06F9/3832 , G06F9/3834 , G06F9/384 , G06F12/0855 , G06F12/0862 , G06F2212/452 , G06F2212/6028
Abstract: A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. At least a store instruction and a subsequent load instruction that access the same memory address in the external memory are identified, based on respective formats of the memory addresses specified in the symbolic expressions. An outcome of at least one of the memory-access instructions is assigned to be served to one or more instructions that depend on the load instruction, from an internal memory in the processor.
Abstract translation: 一种方法在处理器中包括包括存储器访问指令的处理程序代码，其中至少一些存储器访问指令包括根据一个或多个寄存器名称指定外部存储器中的存储器地址的符号表达式。 基于符号表达式中指定的存储器地址的相应格式，至少识别访问外部存储器中相同存储器地址的存储指令和后续加载指令。 存储器访问指令中的至少一个的结果被分配给来自处理器中的内部存储器的取决于加载指令的一个或多个指令。
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