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    PARALLELIZED EXECUTION OF INSTRUCTION SEQUENCES BASED ON PRE-MONITORING
    2.
    发明申请
    PARALLELIZED EXECUTION OF INSTRUCTION SEQUENCES BASED ON PRE-MONITORING 审中-公开
    基于预监测的指令序列并行执行

    公开(公告)号：US20160291982A1

    公开(公告)日：2016-10-06

    申请号：US14673884

    申请日：2015-03-31

    Applicant: CENTIPEDE SEMI LTD.

    Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

    IPC: G06F9/38

    CPC classification number: G06F9/3808 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/46

    Abstract: A method includes, in a processor that processes instructions of program code, processing one or more of the instructions in a first segment of the instructions by a first hardware thread. Upon detecting that an instruction defined as a parallelization point has been fetched for the first thread, a second hardware thread is invoked to process at least one of the instructions in a second segment of the instructions, at least partially in parallel with processing of the instructions of the first segment by the first hardware thread, in accordance with a specification of register access that is indicative of data dependencies between the first and second segments.

    Abstract translation: 一种方法包括在处理程序代码指令的处理器中，通过第一硬件线程处理指令的第一段中的一个或多个指令。 在检测到针对第一线程获取定义为并行化点的指令时，第二硬件线程被调用以在指令的第二段中至少部分地与指令的处理并行地处理指令中的至少一个指令 根据指示第一和第二段之间的数据依赖性的寄存器访问的规范，由第一硬件线程执行第一段。

    FLUSHING IN A PARALLELIZED PROCESSOR
    3.
    发明申请
    FLUSHING IN A PARALLELIZED PROCESSOR 审中-公开

    公开(公告)号：US20180095766A1

    公开(公告)日：2018-04-05

    申请号：US15285555

    申请日：2016-10-05

    Applicant: Centipede Semi Ltd.

    Inventor： Jonathan Friedmann ,  Noam Mizrahi ,  Alberto Mandler

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3861 ,  G06F9/30043 ,  G06F9/3808 ,  G06F9/3863 ,  G06F9/3867

    Abstract: A method includes, in a processor having a pipeline, fetching instructions of program code at run-time, in an order that is different from an order-of-appearance of the instructions in the program code. The instructions are divided into segments having segment identifiers (IDs). An event, which warrants flushing of instructions starting from an instruction belonging to a segment, is detected. In response to the event, at least some of the instructions in the segment that are subsequent to the instruction, and at least some of the instructions in one or more subsequent segments that are subsequent to the segment, are flushed from the pipeline based on the segment IDs.

    PROCESSOR WITH EFFICIENT PROCESSING OF RECURRING LOAD INSTRUCTIONS
    5.
    发明申请
    PROCESSOR WITH EFFICIENT PROCESSING OF RECURRING LOAD INSTRUCTIONS 审中-公开
    处理器能够有效地处理负载指令

    公开(公告)号：US20170010972A1

    公开(公告)日：2017-01-12

    申请号：US14794841

    申请日：2015-07-09

    Applicant: Centipede Semi Ltd.

    Inventor： Noam Mizrahi ,  Jonathan Friedmann

    IPC: G06F12/08 ,  G06F9/30

    CPC classification number: G06F12/0855 ,  G06F9/3826 ,  G06F9/3832 ,  G06F9/3834

    Abstract: A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. At least first and second load instructions that access a same memory address in the external memory are identified in the program code, based on respective formats of the memory addresses specified in the symbolic expressions of the load instructions. An outcome of at least one of the load instructions is assigned to be served from an internal memory in the processor.

    Abstract translation: 一种方法在处理器中包括包括存储器访问指令的处理程序代码，其中至少一些存储器访问指令包括根据一个或多个寄存器名称指定外部存储器中的存储器地址的符号表达式。 基于在加载指令的符号表达式中指定的存储器地址的相应格式，在程序代码中识别访问外部存储器中相同存储器地址的至少第一和第二加载指令。 分配至少一个加载指令的结果从处理器中的内部存储器提供。

    Early termination of segment monitoring in run-time code parallelization
    6.
    发明申请
    Early termination of segment monitoring in run-time code parallelization 审中-公开
    运行时代码并行化提前终止段监控

    公开(公告)号：US20160179536A1

    公开(公告)日：2016-06-23

    申请号：US15007299

    申请日：2016-01-27

    Applicant: Centipede Semi Ltd.

    Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

    IPC: G06F9/30

    CPC classification number: G06F9/3808 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/46 ,  G06F11/30 ,  G06F11/3466 ,  G06F11/348 ,  G06F2201/865 ,  G06F2201/88

    Abstract: A processor includes a processing pipeline including multiple hardware threads and configured to execute software code instructions that are stored in a memory, along with multiple registers, configured to be read and written to by the processing pipeline during execution of the instructions. A monitoring unit monitors the instructions in the processing pipeline and records respective monitoring tables indicating the registers accessed in processing the instructions in different sequences of the instructions, and parallelizes among the hardware threads of the processor, using the respective monitoring tables, execution of repetitions of at least first sequences of the instructions. The monitoring unit is configured to evaluate a termination criterion based on the monitored instructions while monitoring the processing and recording the respective monitoring tables, and upon meeting the termination criterion, to terminate the monitoring before completion of the recording of the respective monitoring tables for at least second sequences of the instructions.

    Abstract translation: 处理器包括处理流水线，其包括多个硬件线程，并被配置为执行存储在存储器中的软件代码指令以及配置为在执行指令期间被处理流水线读取和写入的多个寄存器。 监视单元监视处理流水线中的指令，并且记录指示在指令的不同序列中处理指令时访问的寄存器的各个监视表，并使用相应的监视表来执行处理器的硬件线程，执行重复的 指令的至少第一序列。 监视单元被配置为在监视处理和记录各个监视表的同时监视所监视的指令，并且在满足终止标准时，评估终止标准，以便在完成各个监控表的记录之前至少终止监视 指令的第二个序列。

    Run-time code parallelization with continuous monitoring of repetitive instruction sequences
    7.
    发明授权
    Run-time code parallelization with continuous monitoring of repetitive instruction sequences 有权
    连续监视重复指令序列的运行时代码并行化

    公开(公告)号：US09348595B1

    公开(公告)日：2016-05-24

    申请号：US14578516

    申请日：2014-12-22

    Applicant: Centipede Semi Ltd.

    Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

    IPC: G06F9/30

    CPC classification number: G06F9/3838 ,  G06F9/3851 ,  G06F9/46 ,  G06F11/30 ,  G06F11/3466 ,  G06F2201/865

    Abstract: A method includes, in a processor that executes instructions of program code, monitoring instructions of a repetitive sequence of the instructions that traverses a flow-control trace so as to construct a specification of register access by the monitored instructions. Based on the specification, multiple hardware threads are invoked to execute respective segments of the repetitive instruction sequence at least partially in parallel. Monitoring of the instructions continues in at least one of the segments during execution.

    Abstract translation: 一种方法包括在执行程序代码指令的处理器中监视遍历流程控制轨迹的指令的重复序列的指令，以便构建被监视指令的寄存器访问的规范。 基于该规范，调用多个硬件线程来至少部分地并行地执行重复指令序列的相应段。 在执行期间，至少一个段中的指令的监视继续。

    PROCESSOR WITH EFFICIENT REORDER BUFFER (ROB) MANAGEMENT
    8.
    发明申请
    PROCESSOR WITH EFFICIENT REORDER BUFFER (ROB) MANAGEMENT 审中-公开

    公开(公告)号：US20170344374A1

    公开(公告)日：2017-11-30

    申请号：US15603505

    申请日：2017-05-24

    Applicant: Centipede Semi Ltd.

    Inventor： Jonathan Friedmann ,  Shay Koren

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/30058 ,  G06F9/3855 ,  G06F9/3867

    Abstract: A method includes, in a pipeline of a processor, writing instructions of a single software thread that are pending for execution into a reorder buffer (ROB) in accordance with a single write position, and incrementing the single write position to point to a location in the ROB for a next instruction to be written. The instructions, which were written in accordance with the single write position, are removed from first and second different locations in the ROB, and the first and second locations are incremented.

    PROCESSOR WITH EFFICIENT PROCESSING OF RECURRING LOAD INSTRUCTIONS FROM NEARBY MEMORY ADDRESSES
    10.
    发明申请
    PROCESSOR WITH EFFICIENT PROCESSING OF RECURRING LOAD INSTRUCTIONS FROM NEARBY MEMORY ADDRESSES 有权
    处理器能够有效地处理来自近似存储器地址的负载指令

    公开(公告)号：US20170010971A1

    公开(公告)日：2017-01-12

    申请号：US14794837

    申请日：2015-07-09

    Applicant: Centipede Semi Ltd.

    Inventor： Noam Mizrahi ,  Jonathan Friedmann

    IPC: G06F12/08 ,  G06F9/38 ,  G06F9/30

    CPC classification number: G06F12/0875 ,  G06F8/4442 ,  G06F9/30181 ,  G06F9/30196 ,  G06F9/345 ,  G06F9/35 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3867 ,  G06F12/0862 ,  G06F2212/452 ,  G06F2212/6026

    Abstract: A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. Based on respective formats of the memory addresses specified in the symbolic expressions, a sequence of load instructions that access a predictable pattern of memory addresses in the external memory is identified. At least one cache line that includes a plurality of data values is retrieved from the external memory. Based on the predictable pattern, two or more of the data values that are requested by respective load instructions in the sequence are saved from the cache line to the internal memory. The saved data values are assigned to be served from the internal memory to one or more instructions that depend on the respective load instructions.

    Abstract translation: 一种方法在处理器中包括包括存储器访问指令的处理程序代码，其中至少一些存储器访问指令包括根据一个或多个寄存器名称指定外部存储器中的存储器地址的符号表达式。 基于在符号表达式中指定的存储器地址的相应格式，识别访问外部存储器中的可预测的存储器地址模式的加载指令序列。 从外部存储器检索包括多个数据值的至少一个高速缓存行。 基于可预测的模式，将序列中的各个加载指令请求的两个或多个数据值从高速缓存行保存到内部存储器。 保存的数据值被分配为从内部存储器提供到依赖于相应负载指令的一个或多个指令。

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