公开(公告)号：US20170123798A1

公开(公告)日：2017-05-04

申请号：US15077940

申请日：2016-03-23

Applicant: Centipede Semi Ltd.

Inventor： Jonathan Friedmann ,  Ido Goren ,  Shay Koren ,  Noam Mizrahi ,  Alberto Mandler

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F8/443 ,  G06F9/30061 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30079 ,  G06F9/3808 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3867 ,  G06F9/45516

Abstract: A method includes, in a processor, processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block of instructions is identified in the instructions flowing via the pipeline. The first block includes at least first and second conditional branch instructions that conditionally diverge execution of the instructions into a plurality of flow-control traces that differ from one another in multiple instructions and converge at a given instruction. A second block of instructions, which is logically equivalent to the first block but replaces the plurality of flow-control traces by a reduced set of one or more flow-control traces, having fewer flow-control traces than the first block, is created by the processor at runtime. The pipeline is caused to execute the second block instead of the first block.

公开(公告)号：US20160291982A1

公开(公告)日：2016-10-06

申请号：US14673884

申请日：2015-03-31

Applicant: CENTIPEDE SEMI LTD.

Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC: G06F9/38

CPC classification number: G06F9/3808 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/46

Abstract: A method includes, in a processor that processes instructions of program code, processing one or more of the instructions in a first segment of the instructions by a first hardware thread. Upon detecting that an instruction defined as a parallelization point has been fetched for the first thread, a second hardware thread is invoked to process at least one of the instructions in a second segment of the instructions, at least partially in parallel with processing of the instructions of the first segment by the first hardware thread, in accordance with a specification of register access that is indicative of data dependencies between the first and second segments.

Abstract translation: 一种方法包括在处理程序代码指令的处理器中，通过第一硬件线程处理指令的第一段中的一个或多个指令。 在检测到针对第一线程获取定义为并行化点的指令时，第二硬件线程被调用以在指令的第二段中至少部分地与指令的处理并行地处理指令中的至少一个指令 根据指示第一和第二段之间的数据依赖性的寄存器访问的规范，由第一硬件线程执行第一段。

公开(公告)号：US20170277544A1

公开(公告)日：2017-09-28

申请号：US15620837

申请日：2017-06-13

Applicant: CENTIPEDE SEMI LTD.

Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC: G06F9/38 ,  G06F11/30

CPC classification number: G06F9/3861 ,  G06F9/3808 ,  G06F9/3838 ,  G06F9/3851 ,  G06F11/1402 ,  G06F11/30 ,  G06F11/302 ,  G06F11/3055 ,  G06F11/3065 ,  G06F11/3466

Abstract: A processor includes an execution pipeline and monitoring circuity. The execution pipeline is configured to execute instructions of program code. The monitoring circuity is configured to monitor the instructions in a segment of a repetitive sequence of the instructions so as to construct a specification of register access by the monitored instructions, to parallelize execution of the repetitive sequence based on the corrected specification, and to terminate monitoring of the instructions and discard the specification in response to detecting a branch mis-prediction in the monitored instructions.

公开(公告)号：US20160306633A1

公开(公告)日：2016-10-20

申请号：US14690424

申请日：2015-04-19

Applicant: Centipede Semi Ltd.

Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3861 ,  G06F9/3808 ,  G06F9/382 ,  G06F9/3832 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3875 ,  G06F9/455 ,  G06F9/46 ,  G06F12/0833

Abstract: A method includes, in a processor that processes instructions of program code, processing a first segment of the instructions. One or more destination registers are identified in the first segment using an approximate specification of register access by the instructions. Respective values of the destination registers are made available to a second segment of the instructions only upon verifying that the values are valid for readout by the second segment in accordance with the approximate specification. The second segment is processed at least partially in parallel with processing of the first segment, using the values made available from the first segment.

Abstract translation: 一种方法包括在处理程序代码指令的处理器中处理指令的第一段。 使用指令的寄存器访问的近似规范，在第一段中标识一个或多个目的地寄存器。 目的地寄存器的相应值仅在验证该值对于根据近似规范由第二段读出有效时才可用于指令的第二段。 使用从第一段获得的值，至少部分地与第一段的处理并行处理第二段。

公开(公告)号：US09208066B1

公开(公告)日：2015-12-08

申请号：US14637418

申请日：2015-03-04

Applicant: Centipede Semi Ltd.

Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC: G06F9/45 ,  G06F11/36 ,  G06F9/44 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F11/3024 ,  G06F8/452 ,  G06F8/456 ,  G06F9/48 ,  G06F11/3404

Abstract: A method includes, in a processor that executes instructions of program code, identifying a region of the code containing one or more segments of the instructions that are at least partially repetitive. The instructions in the region are monitored, and an approximate specification of register access by the monitored instructions is constructed for the region. Execution of the segments in the region is parallelized using the specification.

Abstract translation: 一种方法包括在执行程序代码的指令的处理器中，识别包含至少部分重复的指令的一个或多个段的代码的区域。 监视该区域中的指令，并为该区域构建受监视指令的寄存器访问的近似规范。 使用规范并行执行区域中的段。

公开(公告)号：US20180095766A1

公开(公告)日：2018-04-05

申请号：US15285555

申请日：2016-10-05

Applicant: Centipede Semi Ltd.

Inventor： Jonathan Friedmann ,  Noam Mizrahi ,  Alberto Mandler

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30043 ,  G06F9/3808 ,  G06F9/3863 ,  G06F9/3867

Abstract: A method includes, in a processor having a pipeline, fetching instructions of program code at run-time, in an order that is different from an order-of-appearance of the instructions in the program code. The instructions are divided into segments having segment identifiers (IDs). An event, which warrants flushing of instructions starting from an instruction belonging to a segment, is detected. In response to the event, at least some of the instructions in the segment that are subsequent to the instruction, and at least some of the instructions in one or more subsequent segments that are subsequent to the segment, are flushed from the pipeline based on the segment IDs.

公开(公告)号：US09858075B2

公开(公告)日：2018-01-02

申请号：US14960385

申请日：2015-12-06

Applicant: Centipede Semi Ltd.

Inventor： Omri Tennenhaus ,  Noam Mizrahi ,  Alberto Mandler

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3005 ,  G06F9/30098 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863

Abstract: A method includes, in a processor that processes multiple segments of a sequence of instructions of program code, wherein each segment is defined as either speculative or non-speculative, dispatching the instructions of the segments into at least one instruction buffer. The instructions of the segments are executed, and, in each segment, at least some of the executed instructions of the segment are speculatively-committed from the at least one instruction buffer independently of any other segment. Dispatching the instructions includes dispatching the instructions of a first segment into a first region of the at least one instruction buffer, and dispatching the instructions of a second segment, which occurs later in the program code than the first segment, into a second region of the at least one instruction buffer before all the instructions of the first segment have been dispatched into the first region.

公开(公告)号：US20170161066A1

公开(公告)日：2017-06-08

申请号：US14960385

申请日：2015-12-06

Applicant: Centipede Semi Ltd.

Inventor： Omri Tennenhaus ,  Noam Mizrahi ,  Alberto Mandler

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3005 ,  G06F9/30098 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863

Abstract: A method includes, in a processor that processes multiple segments of a sequence of instructions of program code, wherein each segment is defined as either speculative or non-speculative, dispatching the instructions of the segments into at least one instruction buffer. The instructions of the segments are executed, and, in each segment, at least some of the executed instructions of the segment are speculatively-committed from the at least one instruction buffer independently of any other segment. Dispatching the instructions includes dispatching the instructions of a first segment into a first region of the at least one instruction buffer, and dispatching the instructions of a second segment, which occurs later in the program code than the first segment, into a second region of the at least one instruction buffer before all the instructions of the first segment have been dispatched into the first region.

公开(公告)号：US20170123797A1

公开(公告)日：2017-05-04

申请号：US15077936

申请日：2016-03-23

Applicant: Centipede Semi Ltd.

Inventor： Jonathan Friedmann ,  Ido Goren ,  Shay Koren ,  Noam Mizrahi ,  Alberto Mandler

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F8/443 ,  G06F9/30061 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30079 ,  G06F9/3808 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3867 ,  G06F9/45516

Abstract: A method includes, in a processor, processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block of instructions is identified in the instructions flowing via the pipeline. The first block includes a conditional branch instruction that conditionally diverges execution of the instructions into at least first and second flow-control traces that differ from one another in multiple instructions and converge at a given instruction that is again common to the first and second flow-control traces. A second block of instructions, which is logically equivalent to the first block but replaces the first and second flow-control traces by a single flow-control trace, is created by the processor at runtime. The pipeline is caused to execute the second block instead of the first block.

公开(公告)号：US20160179536A1

公开(公告)日：2016-06-23

申请号：US15007299

申请日：2016-01-27

Applicant: Centipede Semi Ltd.

Inventor： Noam Mizrahi ,  Alberto Mandler ,  Shay Koren ,  Jonathan Friedmann

IPC: G06F9/30

CPC classification number: G06F9/3808 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/46 ,  G06F11/30 ,  G06F11/3466 ,  G06F11/348 ,  G06F2201/865 ,  G06F2201/88

Abstract: A processor includes a processing pipeline including multiple hardware threads and configured to execute software code instructions that are stored in a memory, along with multiple registers, configured to be read and written to by the processing pipeline during execution of the instructions. A monitoring unit monitors the instructions in the processing pipeline and records respective monitoring tables indicating the registers accessed in processing the instructions in different sequences of the instructions, and parallelizes among the hardware threads of the processor, using the respective monitoring tables, execution of repetitions of at least first sequences of the instructions. The monitoring unit is configured to evaluate a termination criterion based on the monitored instructions while monitoring the processing and recording the respective monitoring tables, and upon meeting the termination criterion, to terminate the monitoring before completion of the recording of the respective monitoring tables for at least second sequences of the instructions.

Abstract translation: 处理器包括处理流水线，其包括多个硬件线程，并被配置为执行存储在存储器中的软件代码指令以及配置为在执行指令期间被处理流水线读取和写入的多个寄存器。 监视单元监视处理流水线中的指令，并且记录指示在指令的不同序列中处理指令时访问的寄存器的各个监视表，并使用相应的监视表来执行处理器的硬件线程，执行重复的 指令的至少第一序列。 监视单元被配置为在监视处理和记录各个监视表的同时监视所监视的指令，并且在满足终止标准时，评估终止标准，以便在完成各个监控表的记录之前至少终止监视 指令的第二个序列。