公开(公告)号：US07169701B2

公开(公告)日：2007-01-30

申请号：US10882058

申请日：2004-06-30

Applicant: Chen-Nan Yeh ,  Tsiao-Chen Wu ,  Chao-Cheng Chen

Inventor： Chen-Nan Yeh ,  Tsiao-Chen Wu ,  Chao-Cheng Chen

IPC: H01L21/4763

CPC classification number: H01L21/7682 ,  H01L21/76801 ,  H01L21/76808 ,  H01L2221/1026 ,  H01L2221/1031

Abstract: A method for forming a dual damascene including providing a first dielectric insulating layer including a via opening; forming an organic dielectric layer over the first IMD layer to include filling the via opening; forming a hardmask layer over the organic dielectric layer; photolithographically patterning and dry etching the hardmask layer and organic dielectric layer to leave a dummy portion overlying the via opening; forming an oxide liner over the dummy portion; forming a second dielectric insulating layer over the oxide liner to surround the dummy portion; planarizing the second dielectric insulating layer to expose the upper portion of the dummy portion; and, removing the organic dielectric layer to form a dual damascene opening including the oxide liner lining trench line portion sidewalls.

Abstract translation: 一种用于形成双镶嵌的方法，包括提供包括通孔的第一介电绝缘层; 在所述第一IMD层上形成有机介电层以包括填充所述通孔; 在所述有机介电层上形成硬掩模层; 光刻图案化和干蚀刻硬掩模层和有机电介质层以留下覆盖通孔开口的虚拟部分; 在所述虚拟部分上形成氧化物衬垫; 在所述氧化物衬垫上形成围绕所述虚拟部分的第二介电绝缘层; 平面化第二介电绝缘层以暴露虚设部分的上部; 并且去除有机电介质层以形成包括氧化物衬里衬里沟槽部分侧壁的双镶嵌开口。

公开(公告)号：US20050106856A1

公开(公告)日：2005-05-19

申请号：US10714304

申请日：2003-11-14

Applicant: Chao-Cheng Chen ,  Chen-Nan Yeh ,  Chien-Chung Fu

Inventor： Chao-Cheng Chen ,  Chen-Nan Yeh ,  Chien-Chung Fu

IPC: H01L21/316 ,  H01L21/768 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/311

CPC classification number: H01L21/76808 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/31695

Abstract: A method of forming a dual damascene opening comprising the following steps. A structure having an overlying exposed conductive layer formed thereover is provided. A dielectric layer is formed over the exposed conductive layer. An anti-reflective coating layer is formed over the dielectric layer. The anti-reflective layer and the dielectric layer are etched using a via opening process to form an initial via exposing a portion of the conductive layer. A protective film portion is formed over at least the exposed portion of the conductive layer. The anti-reflective coating layer and the dielectric layer are patterned to reduce the initial via to a reduced via and to form a trench opening substantially centered over the reduced via. The trench opening and the reduced via comprising the dual damascene opening.

Abstract translation: 一种形成双镶嵌开口的方法，包括以下步骤。 提供一种其上形成有上覆的暴露的导电层的结构。 在暴露的导电层上形成电介质层。 在电介质层上形成抗反射涂层。 使用通孔打开工艺蚀刻抗反射层和电介质层，以形成暴露导电层的一部分的初始通孔。 至少在导电层的暴露部分上形成保护膜部分。 将抗反射涂层和电介质层图案化以将初始通孔减小到减小的通孔，并形成基本上位于经过还原通孔的中心的沟槽开口。 沟槽开口和通孔包括双镶嵌开口。

公开(公告)号：US20050101110A1

公开(公告)日：2005-05-12

申请号：US10706382

申请日：2003-11-12

Applicant: Wen-Jui Fu ,  Shang-Ru Sheu ,  Yun-Hung Shen ,  Chao-Cheng Chen

Inventor： Wen-Jui Fu ,  Shang-Ru Sheu ,  Yun-Hung Shen ,  Chao-Cheng Chen

IPC: H01L21/306 ,  H01L21/311 ,  H01L21/322 ,  H01L21/44

CPC classification number: H01L21/31116 ,  H01L21/02046

Abstract: A method of reducing fluorine contamination on a integrated circuit wafer surface is achieved. The method comprises placing an integrated circuit wafer on a cathode stage. The integrated circuit wafer comprises a surface contaminated with fluorine. The integrated circuit wafer is plasma treated with a plasma comprising a reducing gas that forms HF from the fluorine and a bombardment gas that removes the fluorine from the surface. The cathode stage is heated to thereby increase the rate of the fluorine removal.

Abstract translation: 实现了降低集成电路晶片表面上的氟污染的方法。 该方法包括将集成电路晶片放置在阴极级上。 集成电路晶片包括被氟污染的表面。 集成电路晶片用包括从氟形成HF的还原气体的等离子体等离子体处理，以及从表面除去氟的轰击气体。 加热阴极级，从而提高除氟率。

公开(公告)号：US06383943B1

公开(公告)日：2002-05-07

申请号：US09687160

申请日：2000-10-16

Applicant: Chao-Cheng Chen ,  Jen-Cheng Liu ,  Jyu-Horng Shieh ,  Chia-Shiung Tsai ,  Bor-Shyang Lin

Inventor： Chao-Cheng Chen ,  Jen-Cheng Liu ,  Jyu-Horng Shieh ,  Chia-Shiung Tsai ,  Bor-Shyang Lin

IPC: H01L21302

CPC classification number: H01L21/76843 ,  H01L21/3105 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829

Abstract: A method for eliminating the problems associated with the discontinuous deposition of the glue layer at the bottom of the via resulting from the notch in the silicon nitride etch stop layer. First conductive layer traces are patterned and a silicon nitride (SiN) etch stop layer is provided overlying the first conductive layer. An inter-metal dielectric (IMD) layer then overlies the entire surface. An anisotropic etch is performed leaving via holes in the IMD layer. This is followed by a second anisotropic etch step to remove the etch stop layer not protected by the IMD layer resulting in the formation a notch at the bottom of the via hole. An important step of the present invention is the elimination of this notch accomplished by nitridizing the surface of the IMD layer. A wet polymer cleaning is performed to remove the nitridized IMD surface and eliminating the notch. A glue layer is conformally applied lining the via hole. A second conductive layer is then deposited and the surface is planarized.

Abstract translation: 一种用于消除与在氮化硅蚀刻停止层中由凹口产生的通孔底部的胶层不连续沉积相关的问题的方法。 图案化第一导电层迹线，并且覆盖第一导电层提供氮化硅（SiN）蚀刻停止层。 金属间电介质（IMD）层然后覆盖整个表面。 进行各向异性蚀刻，留下IMD层中的通孔。 然后进行第二个各向异性蚀刻步骤以去除不被IMD层保护的蚀刻停止层，从而在通孔的底部形成切口。 本发明的重要步骤是消除通过使IMD层的表面氮化而实现的这个缺口。 执行湿式聚合物清洁以除去氮化的IMD表面并消除凹口。 粘合层适用于衬套通孔。 然后沉积第二导电层并且将表面平坦化。

公开(公告)号：US06297168B1

公开(公告)日：2001-10-02

申请号：US09677068

申请日：2000-09-29

Applicant: Jyu-Horng Shieh ,  Jen-Cheng Liu ,  Chao-Cheng Chen ,  Li-Chi Chao ,  Chia-Shia Tsai

Inventor： Jyu-Horng Shieh ,  Jen-Cheng Liu ,  Chao-Cheng Chen ,  Li-Chi Chao ,  Chia-Shia Tsai

IPC: H01L213065

CPC classification number: H01L21/7681 ,  H01L21/31116

Abstract: Within a method for etching a trench within a silicon oxide layer there is first provided a substrate. There is then formed over the substrate a silicon oxide layer. There is then formed over the silicon oxide layer a masking layer. There is then etched, while employing a plasma etch method in conjunction with the masking layer as an etch mask layer, the silicon oxide layer to form an etched silicon oxide layer defining a trench. Within the method, the plasma etch method employs an etchant gas composition comprising: (1) octafluorocyclobutane; and (2) at least one of carbon tetrafluoride, difluoromethane, hexafluoroethane and oxygen; but excluding (3) a carbon and oxygen containing gas.

Abstract translation: 在氧化硅层内蚀刻沟槽的方法中，首先提供衬底。 然后在衬底上形成氧化硅层。 然后在氧化硅层上形成掩模层。 然后蚀刻，同时使用等离子体蚀刻方法结合掩模层作为蚀刻掩模层，氧化硅层形成蚀刻氧化硅层，限定沟槽。 在该方法中，等离子体蚀刻方法采用蚀刻剂气体组合物，其包含：（1）八氟环丁烷; 和（2）四氟化碳，二氟甲烷，六氟乙烷和氧中的至少一种; 但不包括（3）含碳和含氧气体。

公开(公告)号：US06277752B1

公开(公告)日：2001-08-21

申请号：US09342040

申请日：1999-06-28

Applicant: Chao-Cheng Chen

Inventor： Chao-Cheng Chen

IPC: H01L21302

CPC classification number: H01L21/76224 ,  H01L21/3081

Abstract: A method for forming a patterned hard mask layer. There is first provided a substrate. There is then formed over the substrate a blanket hard mask layer formed of a hard mask material susceptible to etching within a first plasma etch method, where the first plasma etch method employs a first etchant gas composition which upon plasma activation forms an active fluorine containing etchant species. There is then formed over the blanket hard mask layer a patterned photoresist layer. There is then etched, while employing the first plasma etch method in conjunction with the patterned photoresist layer as a first etch mask layer, the blanket hard mask layer to form a patterned hard mask layer which defines a first aperture. The first plasma etch method also forms at the bottom of the first aperture defined by the patterned hard mask layer a residue. Finally, there is then etched, while employing a second etch method, the residue from the bottom of the first aperture. The patterned hard mask layer may then be employed for forming within a microelectronic layer, such as a semiconductor substrate, formed beneath the microelectronic layer, an aperture, such as an isolation trench, while employing a third plasma etch method. There may then be formed within the aperture a planarized aperture fill layer, such as a planarized trench isolation region, with enhanced planarity.

Abstract translation: 一种形成图案化硬掩模层的方法。 首先提供基板。 然后在衬底上形成由在第一等离子体蚀刻方法中容易蚀刻的硬掩模材料形成的橡皮布硬掩模层，其中第一等离子体蚀刻方法采用第一蚀刻剂气体组合物，其在等离子体激活时形成活性含氟蚀刻剂 种类。 然后在橡皮布硬掩模层上形成图案化的光致抗蚀剂层。 然后蚀刻，同时采用第一等离子体蚀刻方法结合图案化的光致抗蚀剂层作为第一蚀刻掩模层，橡皮布硬掩模层以形成限定第一孔的图案化硬掩模层。 第一等离子体蚀刻方法也形成在由图案化的硬掩模层限定的第一孔的底部残留物处。 最后，然后在使用第二蚀刻方法的同时蚀刻来自第一孔径底部的残留物。 然后可以使用图案化的硬掩模层，在采用第三等离子体蚀刻方法的同时，在微电子层（例如形成在微电子层下方的半导体衬底），孔（例如隔离沟槽）之间形成。 然后可以在孔内形成具有增强的平面度的平坦化孔填充层，例如平坦化的沟槽隔离区域。

公开(公告)号：US6040248A

公开(公告)日：2000-03-21

申请号：US104032

申请日：1998-06-24

Applicant: Chao-Cheng Chen ,  Ming-Hsin Huang ,  Hun-Jan Tao ,  Chia-Shiung Tsai

Inventor： Chao-Cheng Chen ,  Ming-Hsin Huang ,  Hun-Jan Tao ,  Chia-Shiung Tsai

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/302 ,  C23F1/02 ,  H01L21/461

CPC classification number: H01L21/31138 ,  H01L21/76802

Abstract: A process for plasma etching of contact and via openings in low-k organic polymer dielectric layers is described which overcomes problems of sidewall bowing and hardmask pattern deterioration by etching the organic layer in a high density plasma etcher with a chlorine/inert gas plasma. By adding chlorine to the oxygen/inert gas plasma, the development of an angular aspect or faceting of the hardmask pattern edges by ion bombardment is abated. Essentially vertical sidewalls are obtained in the openings etched in the organic polymer layer while hardmask pattern integrity is maintained. The addition of a passivating agent such as nitrogen, BCl.sub.3, or CHF.sub.3 to the etchant gas mixture further improves the sidewall profile by reducing bowing through protective polymer formation.

Abstract translation: 描述了一种用于等离子体蚀刻低k有机聚合物介电层中的接触和通孔开口的方法，其通过用氯/惰性气体等离子体在高密度等离子体蚀刻机中蚀刻有机层来克服侧壁弯曲和硬掩模图案劣化的问题。 通过向氧/惰性气体等离子体中加入氯，减少了通过离子轰击形成硬掩模图案边缘的角度方面或刻面。 在保持硬掩模图案完整性的同时，在有机聚合物层中蚀刻的开口中获得基本垂直的侧壁。 钝化剂如氮气，BCl3或CHF3添加到蚀刻剂气体混合物中，通过减少通过保护性聚合物形成的弯曲来进一步改善侧壁轮廓。

公开(公告)号：US12220425B2

公开(公告)日：2025-02-11

申请号：US17455033

申请日：2021-11-16

Applicant: Chao-Cheng Chen

Inventor： Chao-Cheng Chen

IPC: A61K31/716 ,  A61K9/70 ,  A61K35/74 ,  A61P1/04

Abstract: Provided is a method of preventing or treating gastroesophageal reflux disease, including administering to an subject in need thereof a composition including a plurality of fibers formed of β-1-4-glucan, wherein the fibers have a diameter between 15 nm and 35 nm and a mean length of between 1.5 μm and 3.5 μm.

公开(公告)号：US09991375B2

公开(公告)日：2018-06-05

申请号：US13484047

申请日：2012-05-30

Applicant: Jr-Jung Lin ,  Chih-Han Lin ,  Jin-Aun Ng ,  Ming-Ching Chang ,  Chao-Cheng Chen

Inventor： Jr-Jung Lin ,  Chih-Han Lin ,  Jin-Aun Ng ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/78 ,  H01L21/283 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/78 ,  H01L21/283 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode.

公开(公告)号：US09595443B2

公开(公告)日：2017-03-14

申请号：US13277642

申请日：2011-10-20

Applicant: Ming Zhu ,  Hui-Wen Lin ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

Inventor： Ming Zhu ,  Hui-Wen Lin ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

IPC: H01L21/70 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/42376 ,  H01L29/4966

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.

Abstract translation: 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括：衬底，包括围绕并分离P活性区域和N-有源区域的隔离区域; 在P-活性区域上的P金属栅电极，并且在隔离区域上延伸，其中P金属栅电极包括P功函数金属和P功函数金属与衬底之间的含氧TiN层; 以及N型金属栅电极，其在N-有源区上方并在隔离区上方延伸，其中N型金属栅电极包括N功函数金属和N功函数金属与衬底之间的富氮TiN层 其中富氮TiN层在隔离区域上连接到含氧TiN层。