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公开(公告)号：US20240154592A1
公开(公告)日：2024-05-09
申请号：US18505734
申请日：2023-11-09
Inventor： Andrew J. HOWLETT , Michael CHANDLER-PAGE , David P. SINGLETON , Erich P. ZWYSSIG , Craig MCADAM
CPC classification number: H03G3/30 , H03F3/04 , H03G2201/103
Abstract: An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage, wherein the gain update circuitry comprises level detection circuitry configured to determine a signal level of the first input signal or the first output signal.
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公开(公告)号：US20240097633A1
公开(公告)日：2024-03-21
申请号：US18521667
申请日：2023-11-28
Inventor： David P. SINGLETON , Andrew J. HOWLETT , John B. BOWLERWELL
IPC: H03F3/45
CPC classification number: H03F3/45659 , H03F3/45179 , H03F3/45645 , H03F2200/03 , H03F2203/45084 , H03F2203/45402 , H03F2203/45592
Abstract: The present disclosure relates to circuitry comprising audio amplifier circuitry for receiving an audio signal to be amplified; and first and second output nodes for outputting first and second differential output signals. The circuitry further comprises common mode buffer circuitry configured to receive a common mode voltage and to selectively output the common mode voltage to the first and second output nodes.
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公开(公告)号：US20230353111A1
公开(公告)日：2023-11-02
申请号：US17982864
申请日：2022-11-08
Inventor： Andrew J. HOWLETT , Michael CHANDLER-PAGE , David P. SINGLETON , Erich P. ZWYSSIG
CPC classification number: H03G3/30 , H03F3/04 , H03G2201/103
Abstract: An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage.
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公开(公告)号：US20210232165A1
公开(公告)日：2021-07-29
申请号：US17140754
申请日：2021-01-04
Inventor： John B. BOWLERWELL , Andrew J. HOWLETT , Graeme S. ANGUS , Andrei DUMITRIU
Abstract: The present disclosure relates to circuitry for selecting a bias voltage to output at a bias voltage output node of the circuitry. The circuitry comprises a first circuit node configured to receive a first voltage from a first, unregulated, voltage source and a second circuit node configured to receive a second voltage from a second, regulated, voltage source. A switch arrangement configured to selectively couple the bias voltage output node to the first circuit node or the second circuit node is also provided.
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