公开(公告)号：US20240154592A1

公开(公告)日：2024-05-09

申请号：US18505734

申请日：2023-11-09

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Andrew J. HOWLETT ,  Michael CHANDLER-PAGE ,  David P. SINGLETON ,  Erich P. ZWYSSIG ,  Craig MCADAM

IPC: H03G3/30 ,  H03F3/04

CPC classification number: H03G3/30 ,  H03F3/04 ,  H03G2201/103

Abstract: An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage, wherein the gain update circuitry comprises level detection circuitry configured to determine a signal level of the first input signal or the first output signal.

公开(公告)号：US20230088252A1

公开(公告)日：2023-03-23

申请号：US17993638

申请日：2022-11-23

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Craig MCADAM ,  Jonathan TAYLOR ,  Douglas MACFARLANE ,  John KERR ,  James MUNGER ,  John PAVELKA ,  Steven A. ATHERTON

IPC: H01L23/498 ,  H01L23/00

Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.

公开(公告)号：US20220246514A1

公开(公告)日：2022-08-04

申请号：US17245259

申请日：2021-04-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Craig MCADAM ,  Jonathan TAYLOR ,  Douglas MACFARLANE ,  John KERR ,  James MUNGER ,  John PAVELKA ,  Steven A. ATHERTON

IPC: H01L23/498 ,  H01L23/00

Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.