Abstract:
A piezoelectric resonator membrane having a thickness in the range of 200 nm to 500 nm wherein the thickness may be controlled to within 1%; the membrane being sandwiched between electrodes to create a resonator, wherein at least one of the electrodes comprises aluminum thereby minimizing damping due to the weight of the electrode.
Abstract:
A filter package comprising an array of piezoelectric films comprising an array of mixed single crystals that each comprise doped Aluminum Nitride, typically AlxGa(1-x)N or ScxAl(1-x)N, that is sandwiched between an array of lower electrodes and an array of upper electrodes comprising metal layers and silicon membranes with cavities thereover: the array of lower electrodes being coupled to an interposer with a first cavity between the array of lower electrodes and the interposer; the array of silicon membranes having a known thickness and attached over the array of upper electrodes with an array of upper cavities, each upper cavity between a silicon membrane of the array and a common silicon cover; each upper cavity aligned with a piezoelectric film, an upper electrode and silicon membrane, the upper cavities having side walls comprising SiO2; the individual piezoelectric films, their upper electrodes and silicon membranes thereover being separated from adjacent piezoelectric films, upper electrodes and silicon membranes by a passivation material.
Abstract:
A multilayer electronic support structure comprising a plurality of layers extending in an X-Y plane consisting of a dielectric material surrounding metal via posts that conduct in a Z direction perpendicular to the X-Y plane, wherein a stacked via structure crossing at least two via layers of the plurality of layers comprises at least two via posts in neighboring via layers wherein the at least two stacked via posts in neighboring layers have different dimensions in the X-Y plane, such that the stacked via structure tapers.
Abstract:
A multilayer electronic structure comprising a plurality of dielectric layers extending in an X-Y plane and comprising at least one coaxial pair of stacked posts extending through at least one dielectric layer in a Z direction that is substantially perpendicular to the X-Y plane, wherein the coaxial pair of stacked via posts comprises a central post surrounded by a torroidal via post separated from the central post by a separating tube of dielectric material.
Abstract:
A method of fabricating a free standing membrane comprising a via array in a dielectric for use as a precursor in the construction of superior electronic support structures, comprising the stages: I—Fabricating a membrane comprising conductive vias in a dielectric surround on a sacrificial carrier, and II—Detaching the membrane from the sacrificial carrier to form a free standing laminated array, and a method of fabricating an electronic substrate based on such a membrane comprising at least the stages of: (I) Fabricating a membrane comprising conductive vias in a dielectric surround on a sacrificial carrier; (II) Detaching the membrane from the sacrificial carrier to form a free standing laminated array; (V) Thinning and planarizing, and (VII) Terminating.
Abstract:
A filter package comprising an array of piezoelectric films sandwiched between an array of upper electrodes and lower electrodes: the individual piezoelectric films and the upper electrodes being separated by a passivation material; the lower electrode being coupled to an interposer with a first cavity between the lower electrodes and the interposer; the filter package further comprising a silicon wafer of known thickness attached over the upper electrodes with an array of upper cavities between the silicon wafer and a silicon cover; each upper cavity aligned with a piezoelectric film in the array of piezoelectric films, the upper cavities having side walls comprising the passivation material.
Abstract:
A signal carrier for carrying a signal in a direction within the X-Y plane of a multilayer composite electronic structure comprising a plurality of dielectric layers extending in an X-Y plane, the signal carrier comprising a first transmission line comprising a lower continuous metallic layer and further comprising a row of metallic via posts coupled to the continuous metal layer, wherein the transmission line is separated by a dielectric material from an underlying reference plane.
Abstract:
A multilayer electronic support structure comprising at least one pair of adjacent feature layers extending in an X-Y plane that are separated by a via layer; said via layer comprising a dielectric material that is sandwiched between the two adjacent feature layers and at least one constructional element through the dielectric material spanning between said pair of adjacent feature layers in a Z direction perpendicular to the X-Y plane; wherein said at least one constructional element is characterized by having a long dimension in the X-Y plane that is at least 3 times as long as a short dimension in the X-Y plane and wherein the at least one constructional element is fully encapsulated within the dielectric material and is electrically isolated from its surrounding.
Abstract:
A laminated multilayer electronic support structure comprising a dielectric with integral vias and feature layers and further comprising a planar metal core characterized by a thickness of less than 100 microns.
Abstract:
A method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (F) applying a protective coating of photoresist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photoresist; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first half stack; (J) applying an insulating layer onto the second hall stack of alternating conductive layers and insulating layers, (K) removing the second base layer, and (L) terminating the substrate by exposing ends of vias on outer surfaces of the stack and applying terminations thereto.