公开(公告)号：US20190214387A1

公开(公告)日：2019-07-11

申请号：US15868058

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Judson R. Holt ,  George Mulfinger ,  Timothy J. McArdle ,  Thomas Merbeth ,  Ömür Aydin ,  Ruilong Xie

IPC: H01L27/092 ,  H01L27/11 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823871 ,  H01L27/1104 ,  H01L29/41775 ,  H01L29/66515

Abstract: One illustrative method disclosed herein includes, among other things, performing at least one etching process to expose at least a portion of an upper surface of a gate electrode of a first transistor device and at least a vertical portion of one side surface of the gate electrode and performing a material growth process to form a conductive gate-to-source/drain (GSD) contact structure that conductively couples the gate electrode of the first transistor device to a source/drain region of the first transistor device, wherein the conductive GSD contact structure comprises a non-single crystal material portion positioned on previously exposed portions of the gate electrode and a single crystal material portion positioned in the source/drain region.

公开(公告)号：US20180286863A1

公开(公告)日：2018-10-04

申请号：US16002070

申请日：2018-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Matthew W. Stoker ,  Mira Park ,  George R. Mulfinger ,  Yinxiao Yang

IPC: H01L27/092 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211

Abstract: The disclosure is directed to an integrated circuit structure. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner conformally coating the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer, wherein the liner includes an electrical insulator.

公开(公告)号：US10020307B1

公开(公告)日：2018-07-10

申请号：US15429502

申请日：2017-02-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Christopher D. Sheraw ,  Timothy J. McArdle ,  Matthew W. Stoker ,  Mira Park ,  George R. Mulfinger ,  Yinxiao Yang

IPC: H01L21/8249 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211

Abstract: The disclosure is directed to an integrated circuit structure and a method of forming the same. The integrated circuit structure may include: a first device region laterally adjacent to a second device region over a substrate, the first device region including a first fin and the second device region including a second fin; a first source/drain epitaxial region substantially surrounding at least a portion of the first fin; a spacer substantially surrounding the first source/drain epitaxial region, the spacer including an opening in a lateral end portion of the spacer such that the lateral end portion of the spacer overhangs a lateral end portion of the first source/drain epitaxial region; and a liner lining the lateral end portion of the first source/drain epitaxial region beneath the overhanging lateral end portion of the spacer.

公开(公告)号：US09947532B2

公开(公告)日：2018-04-17

申请号：US15425338

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Judson R. Holt ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa A. Smith

IPC: H01L21/00 ,  H01L21/20 ,  H01L21/02 ,  H01L21/76 ,  H01L29/06 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/762

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02636 ,  H01L21/02647 ,  H01L21/2022 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76248 ,  H01L21/76294 ,  H01L29/0642 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device can include the following steps: (i) providing an initial sub-assembly including a trench-defining layer having a top surface; (ii) refining the initial sub-assembly into a first trench-cut intermediate sub-assembly by removing material to form an upper tier of a trench extending downward from the top surface of the trench-defining layer, the upper tier of the trench including two lateral trench surfaces and a bottom trench surface; and (iii) refining the first trench-cut intermediate sub-assembly into a second trench-cut intermediate sub-assembly by selectively removing material in a downwards direction starting from the bottom surface of the trench to form a lower tier of the trench, with the selective removal of material leaving at least a first defect blocking member in the lower tier of the trench.

公开(公告)号：US09893154B2

公开(公告)日：2018-02-13

申请号：US15609295

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy J. McArdle ,  Judson R. Holt ,  Junli Wang

IPC: H01L21/00 ,  H01L29/161 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L29/161 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/04 ,  H01L29/045 ,  H01L29/10 ,  H01L29/1054 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon layer is recessed in a first region of the substrate structure and remains unrecessed in a second region of the substrate structure. A protective layer having a first germanium concentration is formed above the recessed silicon layer in the first region, which extends along a sidewall of the unrecessed silicon layer of the second region. A semiconductor layer having a second germanium concentration is disposed above the protective layer in the first region of the substrate structure, where the first germanium concentration of the protective layer inhibits lateral diffusion of the second germanium concentration from the semiconductor layer in the first region into the unrecessed silicon layer in the second region of the substrate structure.

公开(公告)号：US09577100B2

公开(公告)日：2017-02-21

申请号：US14305543

申请日：2014-06-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Michael P. Chudzik ,  Eric C. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Kern Rim ,  Henry K. Utomo

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L21/306 ,  H01L29/165

CPC classification number: H01L29/7851 ,  B82Y10/00 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer.

Abstract translation: 一种半导体器件，包括至少一个包含硅的悬浮沟道结构，以及存在于悬挂沟道结构上的栅极结构。 至少一个栅极电介质层存在于悬置沟道结构周围，并且至少一个栅极导体存在于至少一个栅极电介质层上。 源极和漏极结构可以由包括硅和锗的材料组成。 源极和漏极结构通过硅包覆层与悬浮沟道结构的源极和漏极端部接触。

公开(公告)号：US09524986B2

公开(公告)日：2016-12-20

申请号：US14315362

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Ramachandra Divakaruni ,  Judson R. Holt ,  Arvind Kumar ,  Unoh Kwon

IPC: H01L21/02 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L21/306 ,  H01L21/311 ,  H01L29/16 ,  H01L21/3105

CPC classification number: H01L27/1207 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a high-mobility fin field effect transistor (finFET) fin in a silicon semiconductor on insulator (SOI) substrate by trapping crystalline lattice dislocations that occur during epitaxial growth in a recess formed in a semiconductor layer. The crystalline lattice dislocations may remain trapped below a thin isolation layer, thereby reducing device thickness and the need for high-aspect ratio etching and fin formation.

Abstract translation: 本发明一般涉及半导体器件，更具体地说，涉及通过捕获外延期间发生的晶格位错而在绝缘体上硅绝缘体（SOI）衬底上形成高迁移率鳍状场效应晶体管（finFET）鳍的结构和方法 在半导体层中形成的凹部中生长。 结晶晶格位错可以保留在薄的隔离层下方，从而减少器件厚度以及高纵横比蚀刻和鳍形成的需要。

公开(公告)号：US09466616B2

公开(公告)日：2016-10-11

申请号：US15054951

申请日：2016-02-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric C. T. Harley ,  Judson R. Holt ,  Yue Ke ,  Timothy J. McArdle ,  Shogo Mochizuki ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.

公开(公告)号：US09287264B1

公开(公告)日：2016-03-15

申请号：US14561395

申请日：2014-12-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Eric C. T. Harley ,  Judson R. Holt ,  Gauri V. Karve ,  Yue Ke ,  Derrick Liu ,  Timothy J. McArdle ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa A. Smith

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/84 ,  H01L29/36 ,  H01L29/20 ,  H01L29/16 ,  H01L27/12

CPC classification number: H01L27/0924 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.

Abstract translation: 本发明的实施例提供了一种外延生长FinFET的方法。 一种方法可以包括提供包括绝缘体和底层的半导体衬底; 使用外延生长在所述半导体衬底上形成沟道层; 将凹槽蚀刻到沟道层中并外延地再生沟道层上的一部分; 蚀刻通道层和底层以形成翅片; 形成栅极结构和一组间隔物; 将源漏区蚀刻到沟道层中; 以及在源极漏极区域中形成源极漏极材料。

公开(公告)号：US10262903B2

公开(公告)日：2019-04-16

申请号：US15630547

申请日：2017-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Yi Qi ,  Hsien-Ching Lo ,  Jianwei Peng

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an N-P boundary spacer structure used with finFET devices and methods of manufacture. The method includes forming a plurality of first fin structures, forming a blocking layer between a first fin structure of the plurality of fin structures and a second fin structure of the plurality of fin structures, and forming an epitaxial material on the first fin structure, while blocking the epitaxial material from extending onto the second fin structure by at least the blocking layer formed between the first fin structure and the second fin structure.