公开(公告)号：US20150279738A1

公开(公告)日：2015-10-01

申请号：US14225529

申请日：2014-03-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gabriel Padron Wells ,  Xiang Hu ,  Guillaume Bouche ,  Andre Labonte

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/40 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/467 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795

Abstract: Embodiments of the present invention provide an improved contact and method of fabrication. A dielectric layer is formed over transistor structures which include gates and source/drain regions. A first etch, which may be a reactive ion etch, is used to partially recess the dielectric layer. A second etch is then used to continue the etch of the dielectric layer to form a cavity adjacent to the gate spacers. The second etch is highly selective to the spacer material, which prevents damage to the spacers during the exposure (opening) of the source/drain regions.

Abstract translation: 本发明的实施例提供了改进的接触和制造方法。 在包括栅极和源极/漏极区域的晶体管结构上形成介电层。 使用可以是反应离子蚀刻的第一蚀刻来部分地凹陷介电层。 然后使用第二蚀刻来继续蚀刻介电层以形成与栅极间隔物相邻的空腔。 第二蚀刻对间隔物材料具有高选择性，这防止了在源极/漏极区域的曝光（打开）期间损坏间隔物。

公开(公告)号：US10770585B2

公开(公告)日：2020-09-08

申请号：US16139917

申请日：2018-09-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Andre Labonte ,  Daniel Chanemougame

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/768 ,  H01L21/28 ,  H01L29/08 ,  H01L29/49 ,  H01L23/532

Abstract: A device including a self-aligned buried contact between spacer liners and isolated from a pull down (PD)/pull-up (PU) shared gate and an n-channel field-effect transistor (NFET) pass gate (PG) gate and method of production thereof. Embodiments include first and second high-k/metal gate (HKMG) structures over a first portion of a substrate, and a third HKMG structure over a second portion of the substrate; an inter-layer dielectric (ILD) over a portion of the substrate and on sidewalls of the first, second and third HKMG structures; a spacer liner on sidewalls of the ILD between the second and third HKMG structures; and a buried contact layer between the spacer liner and in a portion of the substrate.

公开(公告)号：US10014215B2

公开(公告)日：2018-07-03

申请号：US15689413

申请日：2017-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre Labonte ,  Ruilong Xie ,  Xunyuan Zhang

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/535 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/823431 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a high-k dielectric liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the cap. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core and liner at an intermediate portion of the CB trench. The core is selectively etched relative to the liner to extend the CB trench to a bottom at the gate metal. The CB trench is metalized to form a CB contact.

公开(公告)号：US09941278B2

公开(公告)日：2018-04-10

申请号：US15202764

申请日：2016-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre Labonte ,  Ruilong Xie ,  Xunyuan Zhang

IPC: H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L29/45 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/532 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76889 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53209 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the core. The liner is etched to the level of the TS. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core at a shelf portion of the CB trench. The core is etched to extend the CB trench to a bottom at the gate metal. The shelf portion having a larger area than the bottom. The CB trench is metalized to form a CB contact.

公开(公告)号：US09780178B2

公开(公告)日：2017-10-03

申请号：US14731960

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andre Labonte ,  Andreas Knorr

IPC: H01L21/00 ,  H01L29/423 ,  H01L23/535 ,  H01L29/06 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/4232 ,  H01L21/28008 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed herein includes, among other things, forming a gate contact opening in a layer of insulating material, wherein the gate contact opening is positioned at least partially vertically above a active region, the gate contact opening exposing a portion of at least a gate cap layer of a gate structure, performing at least one etching process to remove the gate cap layer and recess a sidewall spacer so as to thereby define a spacer cavity and expose at least an upper surface of a gate electrode within the gate contact opening, filling the spacer cavity with an insulating material while leaving the upper surface of the gate electrode exposed, and forming a conductive gate contact in the gate contact opening.

公开(公告)号：US09490317B1

公开(公告)日：2016-11-08

申请号：US14712388

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre Labonte ,  Ryan Ryoung-han Kim

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/6656 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/78

Abstract: There is set forth herein a gate contact structure for a gate. The gate contact structure can include a first contact layer and a second contact layer. In one embodiment, a gate contact layer can define a contact that provides a gate tie down. In one embodiment, a gate contact layer can have a minimum width larger than a gate length.

Abstract translation: 这里提出了用于门的栅极接触结构。 栅极接触结构可以包括第一接触层和第二接触层。 在一个实施例中，栅极接触层可以限定提供栅极接合的接触。 在一个实施例中，栅极接触层可以具有大于栅极长度的最小宽度。

公开(公告)号：US09478662B2

公开(公告)日：2016-10-25

申请号：US15063604

申请日：2016-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre Labonte ,  Ruilong Xie

IPC: H01L23/02 ,  H01L29/78 ,  H01L29/45

CPC classification number: H01L29/785 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/45 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative device disclosed herein includes, among other things, a dielectric layer disposed above a source/drain region and a gate structure of a transistor, a first conductive contact positioned in the dielectric layer and contacting the gate structure, wherein a first spacer is disposed on a sidewall of the first conductive contact, and a second conductive contact positioned in the dielectric layer and contacting the source/drain region, wherein the first spacer at least partially defines a spacing between the first conductive contact and the second conductive contact.

Abstract translation: 本文公开的一个示例性器件包括设置在源极/漏极区域和晶体管的栅极结构之上的电介质层，位于电介质层中并接触栅极结构的第一导电接触，其中设置第一间隔物 在所述第一导电接触件的侧壁上，以及定位在所述电介质层中并接触所述源极/漏极区域的第二导电接触件，其中所述第一间隔件至少部分地限定所述第一导电接触件和所述第二导电接触件之间的间隔。

公开(公告)号：US09460963B2

公开(公告)日：2016-10-04

申请号：US14225529

申请日：2014-03-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gabriel Padron Wells ,  Xiang Hu ,  Guillaume Bouche ,  Andre Labonte

IPC: H01L21/467 ,  H01L21/768 ,  H01L29/40 ,  H01L21/033 ,  H01L21/308 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/467 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795

Abstract: Embodiments of the present invention provide an improved contact and method of fabrication. A dielectric layer is formed over transistor structures which include gates and source/drain regions. A first etch, which may be a reactive ion etch, is used to partially recess the dielectric layer. A second etch is then used to continue the etch of the dielectric layer to form a cavity adjacent to the gate spacers. The second etch is highly selective to the spacer material, which prevents damage to the spacers during the exposure (opening) of the source/drain regions.

Abstract translation: 本发明的实施例提供了改进的接触和制造方法。 在包括栅极和源极/漏极区域的晶体管结构上形成介电层。 使用可以是反应离子蚀刻的第一蚀刻来部分地凹陷介电层。 然后使用第二蚀刻来继续蚀刻介电层以形成与栅极间隔物相邻的空腔。 第二蚀刻对间隔物材料具有高选择性，这防止了在源极/漏极区域的曝光（打开）期间损坏间隔物。

公开(公告)号：US10249728B2

公开(公告)日：2019-04-02

申请号：US15955989

申请日：2018-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Andre Labonte ,  Ruilong Xie ,  Lars Liebmann ,  Nigel Cave ,  Guillaume Bouche

IPC: H01L29/49 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L21/306 ,  H01L21/84 ,  H01L21/28 ,  H01L27/12 ,  H01L27/092 ,  H01L27/088 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02 ,  H01L29/40 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/108 ,  H01L21/8234

Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.

公开(公告)号：US20190013241A1

公开(公告)日：2019-01-10

申请号：US15641927

申请日：2017-07-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andre Labonte ,  Lars Liebmann ,  Daniel Chane ,  Chanro Park ,  Nigel Cave ,  Vimal Kamineni

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/311 ,  H01L27/088 ,  H01L29/08 ,  H01L23/535 ,  H01L29/06

Abstract: A method of manufacturing a semiconductor device is provided including forming raised source and drain regions on a semiconductor layer, forming a first insulating layer over the semiconductor layer, forming a first contact to one of the source and drain regions in the first insulating layer, forming a second insulating layer over the first contact, forming a trench in the second insulating layer to expose the first contact, removing a portion of the first contact below the trench, thereby forming a recessed surface of the first contact, removing a portion of the first insulating layer, thereby forming a recess in the trench and exposing a portion of a sidewall of the first contact below the recessed surface of the first contact, and filling the trench and the recess formed in the trench with a contact material to form a second contact in contact with the first contact.