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    Producing models for dynamically depleted transistors using systems having simulation circuits
    12.
    发明授权
    Producing models for dynamically depleted transistors using systems having simulation circuits 有权

    公开(公告)号：US11288430B2

    公开(公告)日：2022-03-29

    申请号：US15822661

    申请日：2017-11-27

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Anupam Dutta ,  Tamilmani Ethirajan

    IPC: G06F30/367 ,  G06F30/30

    Abstract: A simulation circuit, that simulates characteristics of transistors is produced to include: an isolation body resistor representing resistance of a channel isolation portion of a transistor; a main body resistor representing resistance of main channel portion of the transistor; an isolation transistor connected to the isolation body resistor; and a body-contact transistor connected to the main body resistor. Simulated data is generated by supplying test inputs to the simulation circuit, while selectively activating either the isolation transistor or the body-contact transistor. Test data is generated by supplying the test inputs to the transistors, and measuring output of the transistors. The simulated data is compared to the test data to identify data differences. The design of the transistors is changed to reduce the data differences. The generation of test data, comparing, and design changes are repeated, until the data differences are within a threshold.

    Semiconductor device integration with an amorphous region
    13.
    发明授权
    Semiconductor device integration with an amorphous region 有权

    公开(公告)号：US12293994B2

    公开(公告)日：2025-05-06

    申请号：US17955225

    申请日：2022-09-28

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Vvss Satyasuresh Choppalli ,  Anupam Dutta ,  Rajendran Krishnasamy ,  Robert Gauthier, Jr. ,  Xiang Xiang Lu ,  Anindya Nath

    IPC: H01L25/07 ,  H01L21/77 ,  H01L23/14 ,  H01L23/522

    Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.

    Semiconductor device including a body contact region and method of forming the same
    15.
    发明授权
    Semiconductor device including a body contact region and method of forming the same 有权

    公开(公告)号：US12199147B2

    公开(公告)日：2025-01-14

    申请号：US17734135

    申请日：2022-05-02

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Vvss Satyasuresh Choppalli ,  Anupam Dutta ,  Aaron Lee Vallett

    IPC: H01L29/10 ,  H01L21/74

    Abstract: The present disclosure relates to a semiconductor device including a substrate, a first region disposed in the substrate, a terminal region disposed in the first region, a body contact region disposed in the first region and spaced apart from the terminal region, a dielectric layer disposed on the substrate over the first region between the terminal region and the body contact region, an electrically conductive layer disposed on the dielectric layer, and a continuous metallic layer disposed on the electrically conductive layer and extending to the body contact region, the continuous metallic layer disposed on the body contact region and in physical contact with a top and side portions of the electrically conductive layer. The semiconductor device may additionally include a body contact interconnect disposed on a portion of the continuous metallic layer over the electrically conductive layer.

    THREE-DIMENSIONAL INTEGRATED CIRCUIT WITH TOP CHIP INCLUDING LOCAL INTERCONNECT FOR BODY-SOURCE COUPLING
    16.
    发明申请
    THREE-DIMENSIONAL INTEGRATED CIRCUIT WITH TOP CHIP INCLUDING LOCAL INTERCONNECT FOR BODY-SOURCE COUPLING 有权

    公开(公告)号：US20240429128A1

    公开(公告)日：2024-12-26

    申请号：US18340220

    申请日：2023-06-23

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Anupam Dutta ,  Satyasuresh VVss Choppalli ,  Rui Tze Toh

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H01L29/78

    Abstract: Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions; a body region on a channel region between the source and drain regions; and a gate structure adjacent to and between the channel region and the dielectric material layers. Alternatively, the transistor includes: a source region between drain regions; a body region on a channel region between the source region and each drain region; and gate structures adjacent to and between the channel regions and the dielectric material layers. The first chip also includes an insulator layer on the transistor opposite the dielectric material layers, a trench in the insulator layer extending to the source and body regions, and a local interconnect at the bottom of the trench.

    Body-contacted field effect transistors configured for test and methods
    19.
    发明授权
    Body-contacted field effect transistors configured for test and methods 有权

    公开(公告)号：US11367790B2

    公开(公告)日：2022-06-21

    申请号：US16551794

    申请日：2019-08-27

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Anupam Dutta ,  Balaji Swaminathan

    IPC: G01R31/00 ,  G01R31/26 ,  G01R31/28 ,  H01L21/84 ,  H01L29/786 ,  H01L27/12 ,  H01L29/10 ,  G06F30/367

    Abstract: Test structures for a body-contacted field effect transistor (BCFET) include: a single-pad structure with body contact and probe pad regions connected to a channel region at first and second connection points with a known separation distance between the connection points; and a multi-pad structure with a body contact region connected to a channel region at a first connection point and multiple probe pad regions connected to the channel region at second connection points that are separated from the first connection point by different separation distances. A method includes: determining separation distance-dependent internal body potentials at the second connection points in response to different bias conditions by using either multiple single-pad structures, each having a different separation distance between the connection points, or by using a multi-pad structure; and based on the separation distance-dependent internal body potentials, generating a model representing the BCFET with body-contacted and floating body devices.

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