公开(公告)号：US20240429208A1

公开(公告)日：2024-12-26

申请号：US18340230

申请日：2023-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Satyasuresh Vvss Choppalli ,  Rui Tze Toh ,  Mei Hui June Goh

IPC: H01L25/07 ,  H01L23/00 ,  H01L25/00

Abstract: Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions, a body region on a channel region between the source and drain regions, and a gate structure adjacent to and between the channel region and the dielectric material layers. An insulator layer is on the transistor opposite the dielectric material layers and includes an opening extending to the body region. Optionally, a semiconductor layer is at the bottom of the opening. A contact extends into the opening to the body region (or to the semiconductor layer thereon, if applicable).

公开(公告)号：US12211929B1

公开(公告)日：2025-01-28

申请号：US18663523

申请日：2024-05-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alexander Derrickson ,  Anupam Dutta ,  John Pekarik ,  Vibhor Jain ,  V V S S Satyasuresh Choppalli ,  Rui Tze Toh ,  Oscar Restrepo

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.

公开(公告)号：US20240429128A1

公开(公告)日：2024-12-26

申请号：US18340220

申请日：2023-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Satyasuresh VVss Choppalli ,  Rui Tze Toh

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H01L29/78

Abstract: Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions; a body region on a channel region between the source and drain regions; and a gate structure adjacent to and between the channel region and the dielectric material layers. Alternatively, the transistor includes: a source region between drain regions; a body region on a channel region between the source region and each drain region; and gate structures adjacent to and between the channel regions and the dielectric material layers. The first chip also includes an insulator layer on the transistor opposite the dielectric material layers, a trench in the insulator layer extending to the source and body regions, and a local interconnect at the bottom of the trench.