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公开(公告)号：US11238928B2
公开(公告)日：2022-02-01
申请号：US17049024
申请日：2019-11-12
Inventor： Xingsheng Wang , Enming Huang , Xiangshui Miao
Abstract: A read-write circuit mainly includes a read circuit and a write circuit. The write circuit comprises: a first voltage selector and a first voltage follower circuit that is electrically connected to the memristor storage array. The read-write circuit further includes a second voltage selector and a second voltage follower circuit that is electrically connected to the memristor storage array. Voltage stable following during bipolar writing is selected through the foregoing selector. Meanwhile, the reading circuit is provided with a variable resistor to select an access mode. The actual read-out voltage and the output voltage passing through the reference resistor under the same read voltage are input into a differential amplifier to obtain read-out data.
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公开(公告)号：US11127901B1
公开(公告)日：2021-09-21
申请号：US16626520
申请日：2018-11-29
Inventor： Xiangshui Miao , Hao Tong , Yushan Shen , Wang Cai
Abstract: A three-dimensional stacked phase change memory and a preparation method thereof are provided. The method comprises: preparing first horizontal electrodes spaced apart from each other on a substrate; preparing first strip-shaped phase change layers, each having a central gap, between the first horizontal electrodes; preparing first selectors in the central gaps of the first strip-shaped phase change layers; preparing a first insulating layer; preparing second strip-shaped phase change layers at same vertical positions on the first insulating layer; preparing second selectors; then preparing horizontally-oriented insulating holes between the horizontal electrodes; and preparing vertical electrodes between the adjacent insulating holes, thereby forming a multilayer stacked phase change memory with a vertical structure.
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公开(公告)号：US09543510B2
公开(公告)日：2017-01-10
申请号：US13917681
申请日：2013-06-14
Inventor： Xiangshui Miao , Hao Tong , Xiaomin Cheng
IPC: H01L45/00
CPC classification number: H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/128 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/148 , H01L45/1608 , H01L45/1625
Abstract: A multi-layer phase change material, including: a multi-layer film structure. The multi-layer film structure includes a plurality of periodic units. The periodic units each includes a first single-layer film phase change material and a second single-layer film phase change material. The first single-layer film phase change material and the second single-layer film phase change material are alternately stacked. The first single-layer film phase change material includes chemical components that are different from chemical components included in the second single-layer film phase change material, or the first single-layer film phase change material includes chemical components that are the same as chemical components included in the second single-layer film phase change material and a percent composition of the chemical components included in the first single-layer film phase change material is different from a percent composition of the chemical components included in the second single-layer film phase change material.
Abstract translation: 一种多层相变材料，包括：多层膜结构。 多层膜结构包括多个周期性单元。 周期性单元各自包括第一单层膜相变材料和第二单层膜相变材料。 第一单层膜相变材料和第二单层膜相变材料交替堆叠。 第一单层膜相变材料包括与第二单层膜相变材料中包含的化学成分不同的化学成分，或者第一单层膜相变材料包含与化学成分相同的化学成分 包含在第二单层膜相变材料中的包含在第一单层膜相变材料中的化学成分的组成百分比与第二单层膜相变中包含的化学成分的组成百分比不同 材料。
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14.发明授权公开(公告)号：US09418733B2
公开(公告)日：2016-08-16
申请号：US14800693
申请日：2015-07-15
Inventor： Xiangshui Miao , Yi Li , Yingpeng Zhong , Lei Xu , Huajun Sun , Xiaohua Xu
CPC classification number: G11C13/0004 , G11C11/005 , G11C11/54 , G11C13/0002 , G11C13/0011 , G11C13/0033 , G11C13/0035 , G11C13/0069 , G11C13/0097 , G11C14/00 , G11C2013/0092 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/143 , H01L45/144
Abstract: A joint short-time and long-time storage device, including a first electrode layer, a functional material layer connected to the first electrode layer, and a second electrode layer connected to the functional material layer. The first electrode layer is made of inert conductive metal, the second electrode layer is made of active conductive metal, and the functional material layer is made of chalcogenide.
Abstract translation: 一种联合的短时和长时间存储装置，包括第一电极层，连接到第一电极层的功能材料层和连接到功能材料层的第二电极层。 第一电极层由惰性导电金属制成，第二电极层由有源导电金属制成，功能材料层由硫族化物制成。
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15.发明授权公开(公告)号：US12207574B1
公开(公告)日：2025-01-21
申请号：US18748017
申请日：2024-06-19
Inventor： Xiaomin Cheng , Haobin Li , Yunhao Luo , Xiangshui Miao
Abstract: The disclosure discloses a reconfigurable heterojunction memristor, a control method, a fabrication method, and an application thereof. The functional layer designed by the disclosure comprises a PN heterojunction of n-AgO and p-Ag2O or a PN heterojunction of n-CuO2 and p-CuO. In the analog type, multiple resistance state performance is exhibited based on charge trapping and releasing, and self-rectification characteristics are exhibited, without the need for a selector, which facilitates large-scale integration; in the digital type, the presence of Ag/Cu ions in the layer helps to form Ag/Cu conductive filaments, the switching threshold voltage is small, and the advantages of fast switching speed and low switching power consumption are provided. The disclosure realizes a PN heterojunction device of an N-type oxide layer and a P-type oxide layer through electrochemical principles, and is analog type-digital type reconfigurable between a self-rectifying analog type device and a digital type device.
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Patent Agency Ranking
公开(公告)号：US12189270B2
公开(公告)日：2025-01-07
申请号：US18577702
申请日：2021-09-07
Inventor： Xiaomin Cheng , Zhuli He , Yunlai Zhu , Han Li , Xiangshui Miao
IPC: G02F3/02 , G11C13/00 , H03K19/173
Abstract: A Y-branch type phase-change all-optical Boolean logic device comprises a waveguide of a Y-branch structure and phase change function units covered over the waveguide. In the logic implementation method, a light pulse having a large power is employed to perform a write operation on the phase change function unit, so that the phase change function unit is heated to generate a crystallization or amorphization phase change, thereby causing a difference in optical properties under two states; the state of the phase change function unit is read by employing a light pulse having a small power, and the state of its phase change material is not changed. By defining input logic signals respectively and defining three operation steps, an operation mode reconfigurable logic can be implemented, and all 16 binary Boolean logic calculations are implemented in a simple structure by means of step-by-step operation.
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17.发明授权公开(公告)号：US11989644B2
公开(公告)日：2024-05-21
申请号：US17259191
申请日：2020-05-28
Inventor： Hao Tong , Qing Hu , Yuhui He , Xiangshui Miao
IPC: G06N3/0464 , G06N3/063 , G11C11/54 , G11C13/00
CPC classification number: G06N3/063 , G11C11/54 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/77
Abstract: The disclosure discloses a three-dimensional (3D) convolution operation device and method based on a 3D phase change memory, which includes a 3D phase change memory, an input control module, a setting module, and an output control module. By using the 3D phase change memory to perform 3D convolution operation, the phase change units on the same bit line constitute a convolution kernel. Based on the multilayer stack structure, the upper and lower electrodes of the 3D phase change memory serve as the information input terminal, and they are convolved after passing through the respective phase change unit arrays, and the result of the convolution operation is superposed on the middle electrode in the form of current, thereby obtaining the sum of the convolution calculation results of the input information of the upper and lower electrodes, such that the 3D convolution operation is completed in one step.
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公开(公告)号：US11830547B2
公开(公告)日：2023-11-28
申请号：US17054529
申请日：2018-11-29
Inventor： Qun Liu , Yewang Wang , Xiangshui Miao , Jian Li
IPC: G11C13/00
CPC classification number: G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/0038
Abstract: A reduced instruction set processor based on a memristor is provided. The memristor is a non-volatile device using a resistor to store “0” and “1” logic while implementing “implication logic” through applying a pair of voltages VCOND/VSET. Various data operations, logic operations, and arithmetic operations may be implemented based on the implication logic. The memristor is a computation and memory fusion device having great potential. A computer processor based on the memristor also becomes the research direction of the next-generation computer processor. The computer processor based on a memristor is designed according to the memory and computation fusion characteristic of the memristor. The processor is different from a traditional computer that must use a special memory and a calculator, and fuses computation and memory. Compared with a traditional computer, the speed, parallelism degree, and power consumption of the computer processor based on the memristor are greatly improved.
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公开(公告)号：US11678495B2
公开(公告)日：2023-06-13
申请号：US17043672
申请日：2019-09-23
Inventor： Hao Tong , Wang Cai , Xiangshui Miao
CPC classification number: H10B63/845 , H10N70/023 , H10N70/231 , H10N70/841 , H10N70/8825 , H10N70/8828 , H10N70/823 , H10N70/826
Abstract: The disclosure belongs to the technical field of microelectronic devices and memories, and discloses a three-dimensional stacked phase change memory and a preparation method thereof. The preparation method includes: preparing a multilayer structure in which horizontal electrode layers and insulating layers are alternately stacked, then performing etching to form trenches and separated three-dimensional strip electrodes, next filling the trenches with an insulating medium, and then forming small holes at the boundary region between the three-dimensional strip electrodes and the insulating medium, thereafter sequentially depositing a phase change material on the walls of the small holes, and filling the small holes with an electrode material to prepare vertical electrodes, so as to obtain a three-dimensional stacked phase change memory stacked in multiple layers. By improving the overall process of the preparation method, the disclosure realizes the establishment of a three-dimensional phase change memory array by using a vertical electrode structure.
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20.发明授权公开(公告)号：US09473137B2
公开(公告)日：2016-10-18
申请号：US14867030
申请日：2015-09-28
Inventor： Xiangshui Miao , Yaxiong Zhou , Yi Li , Huajun Sun
CPC classification number: H03K19/0002 , H03K19/0021 , H03K19/0813 , H03K19/20
Abstract: A non-volatile Boolean logic operation circuit, including: two input ends; an output end; a first resistive switching element M1, the first resistive switching element M including a positive electrode and a negative electrode; and a second resistive switching element M2, the second resistive switching element M2 including a positive electrode and a negative electrode. The negative electrode of the first resistive switching element M1 operates as a first input end of the logic operation circuit. The negative electrode of the second resistive switching element M2 operates as a second input end of the logic operation circuit. The positive electrode of the second resistive switching element M2 is connected to the positive electrode of the first resistive switching element M1, and a connected end thereof operates as the output end of the logic operation circuit.
Abstract translation: 一种非易失性布尔逻辑运算电路，包括：两个输入端; 输出端 第一电阻式开关元件M1，第一电阻式开关元件M包括正极和负极; 和第二电阻开关元件M2，第二电阻开关元件M2包括正极和负极。 第一电阻式开关元件M1的负电极作为逻辑运算电路的第一输入端工作。 第二电阻开关元件M2的负极作为逻辑运算电路的第二输入端工作。 第二电阻开关元件M2的正极与第一电阻式开关元件M1的正极连接，其连接端作为逻辑运算电路的输出端。
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