公开(公告)号：US11769563B2

公开(公告)日：2023-09-26

申请号：US17562778

申请日：2021-12-27

Applicant: IMEC vzw

Inventor： Maarten Rosmeulen

IPC: G11C25/00

CPC classification number: G11C25/00

Abstract: A liquid electrochemical memory device is provided. In one aspect, the device includes a memory region for storing at least two bits, the memory region having a first volume; and a liquid electrolyte region fluidically connected to the memory region, the liquid electrolyte region having a second volume larger than the first volume. The device further includes a working electrode exposed to the memory region, and a counter electrode exposed to the liquid electrolyte region. The device also includes an electrolyte filling the memory region and the liquid electrolyte region, in physical contact with the working electrode and the counter electrode, the electrolyte including at least two conductive species. The device further includes a control unit for biasing the working electrode and the counter electrode.

公开(公告)号：US20200021758A1

公开(公告)日：2020-01-16

申请号：US16511799

申请日：2019-07-15

Applicant: IMEC VZW

Inventor： Maarten Rosmeulen ,  Andreas Suss

IPC: H04N5/357 ,  H01L27/146

Abstract: A pixel architecture comprises: an absorption layer, which is configured to generate charges in response to incident light; a semiconductor charge-transport layer, which is configured to transport the generated charges through the charge-transport layer, wherein one or more doped regions are arranged in the charge-transport layer, wherein the charge-transport layer comprises a bias region and a charge-dispatch region being associated with the bias region; an electric connection connecting to and providing a selectable bias voltage to the bias region; and at least one transfer gate, wherein the doped regions and the bias region are differently biased for driving transport of the generated charges towards the charge-dispatch region, and for controlling, together with the at least one transfer gate, transfer of charges from the charge-dispatch region to a charge node.

公开(公告)号：US09826184B2

公开(公告)日：2017-11-21

申请号：US15182020

申请日：2016-06-14

Applicant: IMEC VZW

Inventor： Maarten Rosmeulen

IPC: H04N5/372 ,  H04N5/345 ,  H04N9/04 ,  B64D47/08 ,  G06T7/20

CPC classification number: H04N5/37206 ,  B64C2201/127 ,  B64D47/08 ,  G06T7/20 ,  G06T2207/10032 ,  G06T2207/30181 ,  H04N5/345 ,  H04N9/045

Abstract: A device for imaging comprising an image sensor is disclosed. The image sensor includes rows and columns of pixels. The image sensor further includes a first control structure for controlling transfer of accumulated electric charges from photo-active regions to transmission regions in pixels. The image sensor further includes a second control structure for controlling transfer of accumulated charge in the transmission region of each row to the adjacent row below. The first and second control structures control the image sensor to alternately transfer accumulated charges in photo-active regions to the transmission regions and transfer charges to the adjacent row below. The control structure includes a plurality of row structures which are arranged to select whether the charge in the photo-active regions of respective rows are added to the transmission region. Each row of pixels is controlled by one of the row structures of the first control structure.

公开(公告)号：US20150115277A1

公开(公告)日：2015-04-30

申请号：US14520763

申请日：2014-10-22

Applicant: IMEC VZW

Inventor： Vasyl Motsnyi ,  Barundeb Dutta ,  Maarten Rosmeulen

IPC: H01L29/20 ,  H01L33/12 ,  H01L21/306 ,  H01L29/201 ,  H01L21/02 ,  H01L33/00 ,  H01L33/32

CPC classification number: H01L29/2003 ,  B24B37/042 ,  H01L21/02002 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/30625 ,  H01L29/201 ,  H01L33/0025 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/32

Abstract: The embodiments disclose a silicon substrate with a group III-V material and a method for fabricating a group III-V material on a silicon substrate. The method involves providing a silicon substrate. A first layer formed atop the silicon substrate, is subsequently patterned to expose the underlying silicon substrate. A group III-V material layer is formed over the patterned first layer and also on the exposed silicon substrate. The group III-V material layer is subjected to chemical mechanical polishing (CMP) to expose the first layer resulting in the formation of a plurality of areas suitable for growing a device layer on the silicon substrate.

Abstract translation: 实施方式公开了具有III-V族材料的硅衬底和在硅衬底上制造III-V族材料的方法。 该方法包括提供硅衬底。 形成在硅衬底顶上的第一层随后被图案化以暴露下面的硅衬底。 在图案化的第一层上以及暴露的硅衬底上形成III-V族材料层。 对III-V族材料层进行化学机械抛光（CMP）以暴露第一层，从而形成适于在硅衬底上生长器件层的多个区域。

公开(公告)号：US20250118547A1

公开(公告)日：2025-04-10

申请号：US18906944

申请日：2024-10-04

Applicant: IMEC VZW

Inventor： Sana Rachidi ,  Geert Van den Bosch ,  Maarten Rosmeulen ,  Silvia Armini

IPC: H01L21/02 ,  H01L21/3105 ,  H01L21/764 ,  H01L21/768

Abstract: According to an aspect, a method of forming a memory structure for a 3D NAND flash memory includes forming a layer stack over a substrate, forming first recessed areas in a sidewall surrounding a memory hole in the layer stack by laterally etching back gate layers of the layer stack from the memory hole, and forming a lateral memory stack in each first recessed areas, by depositing a blocking oxide and, subsequently, a charge trap material. The method also includes forming second recessed areas in the sidewall by laterally etching back the inter-gate spacer layers from the memory hole and forming dummy layers in the second recessed areas. The method also includes lining the sidewall of the memory hole with a liner layer, subjecting the dummy layers to a thermal treatment process adapted to convert each dummy layer into an air gap structure, and forming a tunneling oxide layer in the memory hole, along the liner layer, and a channel layer along the tunneling oxide layer.

公开(公告)号：US20240112737A1

公开(公告)日：2024-04-04

申请号：US18477456

申请日：2023-09-28

Applicant: IMEC VZW

Inventor： Devin Verreck ,  Maarten Rosmeulen

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/16

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/16 ,  G11C2216/02

Abstract: This disclosed technology relates to a programmable NAND flash memory and a method for operating the NAND flash memory. The method comprises applying a first voltage to the first gate and a pass voltage to one or more word lines to allow charge to inject into the channel layer and form charge packets. Each charge packet can be arranged next to one of the second gates. The method further comprises applying a programming voltage to the word lines to move the charge packets from the channel layer into the memory cells associated with the second gates next to which they are arranged.

公开(公告)号：US20230262996A1

公开(公告)日：2023-08-17

申请号：US18169761

申请日：2023-02-15

Applicant: IMEC VZW

Inventor： Maarten Rosmeulen ,  Jiwon Lee ,  Gouri Sankar Kar ,  Swaraj Bandhu Mahato

IPC: H10B99/00

CPC classification number: H10B99/22

Abstract: A charge-coupled device (CCD) memory is provided. In one aspect, the CCD memory is 3D integrated. The CCD memory can include a gate stack with a plurality of gate layers and spacer layers alternatingly arranged one on the other, and a plurality of semiconductor-based channels extending in the stack. The channels may be formed from a semiconductor oxide material. The CCD memory can include dielectric layers, wherein each dielectric layer is arranged between one of the channels and at least one of the gate layers. Each channel of the CCD memory can form, in combination with the gate layers and at least one of the dielectric layers, a string of charge storage capacitors, and each string of charge storage capacitors can be operable as a CCD register. The CCD memory can also include a readout layer, which can include a plurality of readout stages configured to individually readout stored charge from each of the CCD registers.

公开(公告)号：US11462244B2

公开(公告)日：2022-10-04

申请号：US17645107

申请日：2021-12-20

Applicant: IMEC vzw

Inventor： Grim Keulemans ,  Veronique Rochus ,  Maarten Rosmeulen ,  Xavier Rottenberg

IPC: G11B15/40 ,  G11B5/008 ,  G11B15/20 ,  G11B15/26 ,  G11B15/60

Abstract: A storage device configured to store data on a tape is provided. In one aspect, the storage device includes the tape, which is configured to store data, and a data head, which is configured to read and/or write data from and/or to the tape. The storage device further includes an actuator configured to move the tape in a length direction in a step-wise manner. The actuator can include a plurality of pulling electrodes, wherein each pulling electrode can be activated to exert a pulling force on the tape, and a plurality of clamping electrodes, wherein each clamping electrode can be activated to clamp the tape.

公开(公告)号：US10742916B2

公开(公告)日：2020-08-11

申请号：US16094165

申请日：2017-04-06

Applicant: IMEC VZW

Inventor： Jonathan Borremans ,  Nicolaas Tack ,  Maarten Rosmeulen ,  Paul Goetschalckx ,  Piet De Moor

IPC: H04N5/372 ,  H04N5/347 ,  H04N5/378

Abstract: An imaging sensor is disclosed, comprising: a set of at least two charge-coupled device, CCD, sub-arrays, wherein each sub-array comprises pixels arranged in columns and rows, and each pixel being arranged to accumulate an electric charge proportional to an intensity of light incident on the pixel; a time delay and integration, TDI, clocking circuitry for controlling and timing transfer of accumulated electric charges between rows of pixels in a column direction in order to integrate the accumulated electric charges in each column of pixels; wherein each CCD sub-array further comprises a readout row for converting the integrated electric charge of each column of pixels into voltage or current, wherein the readout row comprises transistors enabling readout of the signal by the readout block; and a readout block which is arranged to receive input from selected readout rows and convert the input into digital domain or convert the input to a combined representation of pixel values based on the set of CCD sub-arrays.