公开(公告)号：US09339868B2

公开(公告)日：2016-05-17

申请号：US14247274

申请日：2014-04-08

Applicant: Infineon Technologies AG

Inventor： Joerg Ortner ,  Michael Sorger

IPC: B22D19/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/48 ,  H01L23/00 ,  G03F7/00 ,  B82Y10/00 ,  B82Y40/00 ,  H05K1/02

CPC classification number: B22D19/0072 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/02 ,  H01L21/311 ,  H01L21/486 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02371 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/0502 ,  H01L2224/06182 ,  H01L2224/06188 ,  H01L2224/94 ,  H01L2924/181 ,  H05K1/02 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/308 ,  Y10S977/887 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a method of processing a substrate in accordance with an embodiment, a trench may be formed in the substrate, a stamp device may be disposed at least in the trench; at least one part of the trench that is free from the stamp device may be at least partially filled with trench filling material; and the stamp device may be removed from the trench.

Abstract translation: 在根据实施例的处理衬底的方法中，可以在衬底中形成沟槽，印模器件可以至少设置在沟槽中; 沟槽的至少一部分没有印模装置可以至少部分地填充有沟槽填充材料; 并且邮票装置可以从沟槽中移除。

公开(公告)号：US09126260B2

公开(公告)日：2015-09-08

申请号：US14247282

申请日：2014-04-08

Applicant: Infineon Technologies AG

Inventor： Joerg Ortner ,  Michael Sorger

IPC: B22D19/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/48 ,  H01L23/00 ,  G03F7/00 ,  B82Y10/00 ,  B82Y40/00

CPC classification number: B22D19/0072 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/02 ,  H01L21/311 ,  H01L21/486 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02371 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/0502 ,  H01L2224/06182 ,  H01L2224/06188 ,  H01L2224/94 ,  H01L2924/181 ,  H05K1/02 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/308 ,  Y10S977/887 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a method of processing a substrate in accordance with an embodiment, a trench may be formed in the substrate, imprint material may be deposited at least into the trench, the imprint material in the trench may be embossed using a stamp device, and the stamp device may be removed from the trench.

Abstract translation: 在根据实施例的处理衬底的方法中，沟槽可以形成在衬底中，压印材料可以至少沉积到沟槽中，沟槽中的压印材料可以使用压印装置压印，并且印模 器件可以从沟槽中移除。

公开(公告)号：US20150000149A1

公开(公告)日：2015-01-01

申请号：US13931396

申请日：2013-06-28

Applicant: Infineon Technologies AG

Inventor： Joerg Ortner ,  Josef Campidell ,  Andreas Greiner

IPC: H01L23/544 ,  G01B5/25

CPC classification number: H01L23/544 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An alignment mark definer is configured to provide a geometrical definition for an actual alignment structure to be formed at a temporary surface of a substrate based on a desired appearance of the alignment mark and on an expected alteration of an appearance of the actual alignment structure caused by a deposition material deposited on the temporary surface and the actual alignment structure.

Abstract translation: 对准标记定义器被配置为基于对准标记的期望外观以及由于对准标记的期望外观而导致的实际对准结构的外观提供要在基板的临时表面处形成的实际对准结构的几何定义 沉积在临时表面上的沉积材料和实际对准结构。

公开(公告)号：US20140287566A1

公开(公告)日：2014-09-25

申请号：US14299481

申请日：2014-06-09

Applicant: Infineon Technologies AG

Inventor： Joerg Ortner

IPC: H01L23/544 ,  H01L21/26

CPC classification number: H01L23/544 ,  H01L21/26 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor chip includes a first mark for identifying a position of the chip within an exposure field. The semiconductor chip includes a first matrix in a first layer of the chip and a second mark within the first matrix identifying a position of the exposure field on a wafer.

Abstract translation: 半导体芯片包括用于识别曝光区域内的芯片的位置的第一标记。 半导体芯片包括芯片的第一层中的第一矩阵和第一矩阵内的第二标记，以识别晶片上的曝光场的位置。

公开(公告)号：US20140220257A1

公开(公告)日：2014-08-07

申请号：US14247282

申请日：2014-04-08

Applicant: Infineon Technologies AG

Inventor： Joerg Ortner ,  Michael Sorger

IPC: H01L21/02

CPC classification number: B22D19/0072 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/02 ,  H01L21/311 ,  H01L21/486 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02371 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/0502 ,  H01L2224/06182 ,  H01L2224/06188 ,  H01L2224/94 ,  H01L2924/181 ,  H05K1/02 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/308 ,  Y10S977/887 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a method of processing a substrate in accordance with an embodiment, a trench may be formed in the substrate, imprint material may be deposited at least into the trench, the imprint material in the trench may be embossed using a stamp device, and the stamp device may be removed from the trench.

Abstract translation: 在根据实施例的处理衬底的方法中，沟槽可以形成在衬底中，压印材料可以至少沉积到沟槽中，沟槽中的压印材料可以使用压印装置压印，并且印模 器件可以从沟槽中移除。

公开(公告)号：US20230275033A1

公开(公告)日：2023-08-31

申请号：US18109616

申请日：2023-02-14

Applicant: Infineon Technologies AG

Inventor： Thomas Huber ,  Matthias Kuenle ,  Iris Moder ,  Joerg Ortner

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/54426

Abstract: A semiconductor substrate includes a semiconductor base substrate. An alignment structure is formed on a surface of the semiconductor base substrate. An epitaxial layer is deposited on the surface of the semiconductor base substrate. The alignment structure includes an area of the surface of the semiconductor base substrate that is formed as a groove pattern. Grooves of the groove pattern are aligned with a specific crystallographic direction of the semiconductor base substrate. The specific crystallographic direction provides for a slower epitaxial growth rate on such a groove-patterned base substrate surface area compared to epitaxial growth on a surface of the semiconductor base substrate adjacent to the groove-patterned area.

公开(公告)号：US11189539B2

公开(公告)日：2021-11-30

申请号：US16433278

申请日：2019-06-06

Applicant: Infineon Technologies AG

Inventor： Prashanth Makaram ,  John Cooper ,  Joerg Ortner ,  Stephan Pindl ,  Caterina Travan ,  Alexander Zoepfl

IPC: H01L23/31 ,  H01L21/02

Abstract: An apparatus includes a semiconductor-based substrate with a functional structure that is formed in or on the semiconductor-based substrate. The apparatus includes a frame structure surrounding the functional structure and includes a coating that covers the functional structure and is delimited by the frame structure.

公开(公告)号：US20180267408A1

公开(公告)日：2018-09-20

申请号：US15919989

申请日：2018-03-13

Applicant: Infineon Technologies AG

Inventor： Joerg Ortner ,  Iris Moder ,  Ingo Muri

IPC: G03F7/20 ,  G03F1/42

CPC classification number: G03F7/203 ,  G03F1/00 ,  G03F1/42

Abstract: An exposure method includes projecting a reticle pattern into a first exposure field of a photoresist layer, wherein the reticle pattern includes first and second line patterns on opposite edges of the reticle pattern and wherein at least the first line pattern includes an end section through which light flux decreases outwards. The reticle pattern is further projected into a second exposure field of the photoresist layer, wherein a first tapering projection zone of the end section of the first line pattern in the second exposure field overlaps a projection area of the second line pattern in the first exposure field.

公开(公告)号：US20170309565A1

公开(公告)日：2017-10-26

申请号：US15137431

申请日：2016-04-25

Applicant: Infineon Technologies AG

Inventor： Joerg Ortner ,  John Cooper

IPC: H01L23/525

CPC classification number: H01L23/5256

Abstract: A method for use in manufacturing semiconductor devices includes providing a structured layer on a wafer, and selectively providing a substance on a selected portion of the structured layer. A die comprises a semiconductor device on a substrate, where the semiconductor device includes a substance, and where the substance has a sidewall that is sheer with respect to one or more of a base surface or a top surface of the substrate.

公开(公告)号：US09704748B2

公开(公告)日：2017-07-11

申请号：US14751035

申请日：2015-06-25

Applicant: Infineon Technologies AG

Inventor： Joerg Ortner ,  Michael Roesner ,  Gudrun Stranzl ,  Rudolf Rothmaler

IPC: H01L21/78 ,  H01L21/308 ,  H01L21/3065 ,  G03F1/38

CPC classification number: H01L21/78 ,  G03F1/38 ,  H01L21/3065 ,  H01L21/3083

Abstract: A method of dicing a wafer includes providing a wafer and etching the wafer to singulate die between kerf line segments defined within an interior region of the wafer and to singulate a plurality of wafer edge areas between the kerf line segments and a circumferential edge of the wafer. Each one of the plurality of wafer edge areas is singulated by kerf lines that each extend between one of two endpoints of one of the kerf line segments and the circumferential edge of the wafer.