-
公开(公告)号:US20240355750A1
公开(公告)日:2024-10-24
申请号:US18758992
申请日:2024-06-28
Applicant: Intel Corporation
Inventor: Adel A. ELSHERBINI , Amr ELSHAZLY , Arun CHANDRASEKHAR , Shawna M. LIFF , Johanna M. SWAN
IPC: H01L23/538 , H01L23/00 , H01L25/00
CPC classification number: H01L23/5385 , H01L24/16 , H01L24/17 , H01L25/00 , H01L2224/16225 , H01L2224/1703
Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.
-
公开(公告)号:US20220254754A1
公开(公告)日:2022-08-11
申请号:US17728813
申请日:2022-04-25
Applicant: Intel Corporation
Inventor: Adel A. ELSHERBINI , Henning BRAUNISCH , Aleksandar ALEKSOV , Shawna M. LIFF , Johanna M. SWAN , Patrick MORROW , Kimin JUN , Brennen MUELLER , Paul B. FISCHER
IPC: H01L25/065 , H01L23/498 , H01L25/00
Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.
-
13.
公开(公告)号:US20210225807A1
公开(公告)日:2021-07-22
申请号:US17222815
申请日:2021-04-05
Applicant: Intel Corporation
Inventor: Adel A. ELSHERBINI , Henning BRAUNISCH , Javier SOTO GONZALEZ , Shawna M. LIFF
IPC: H01L25/065 , H01L23/00 , H01L23/538
Abstract: An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.
-
14.
公开(公告)号:US20210194966A1
公开(公告)日:2021-06-24
申请号:US16757751
申请日:2017-12-30
Applicant: Intel Corporation
Inventor: Georgios C. DOGIAMIS , Sasha N. OSTER , Adel A. ELSHERBINI , Erich N. EWY , Johanna M. SWAN , Telesphor KAMGAING
IPC: H04L29/08 , H01P3/08 , H04L5/14 , G08C23/06 , H04B1/3822 , B60R16/023 , B60R16/03
Abstract: Embodiments include a sensor node, an active sensor node, and a vehicle with a communication system that includes sensor nodes. The sensor node include a package substrate, a diplexer/combiner block on the package substrate, a transceiver communicatively coupled to the diplexer/combiner block, and a first mm-wave launcher coupled to the diplexer/combiner block. The sensor node may have a sensor communicatively coupled to the transceiver, the sensor is communicatively coupled to the transceiver by an electrical cable and located on the package substrate. The sensor node may include that the sensor operates at a frequency band for communicating with an electronic control unit (ECU) communicatively coupled to the sensor node. The sensor node may have a filter communicatively coupled to the diplexer/combiner block, the transceiver communicatively coupled to the filter, the filter substantially removes frequencies from RF signals other than the frequency band of the sensor.
-
公开(公告)号:US20190141456A1
公开(公告)日:2019-05-09
申请号:US16096568
申请日:2016-07-01
Applicant: Intel Corporation
Inventor: Georgios C. DOGIAMIS , Feras EID , Adel A. ELSHERBINI , Johanna SWAN , Shawna M. LIFF , Thomas L. SOUNART , Sasha N. OSTER
CPC classification number: H04R17/005 , B06B1/0622 , B06B1/0625 , B06B1/0644 , H04R2201/028
Abstract: Embodiments of the invention include an acoustic transducer device having a base structure that is positioned in proximity to a cavity of an organic substrate, a piezoelectric material in contact with a first electrode of the base structure, and a second electrode in contact with the piezoelectric material. In one example, for a transmit mode, a voltage signal is applied between the first and second electrodes and this causes a stress in the piezoelectric material which causes a stack that is formed with the first electrode, the piezoelectric material, and the second electrode to vibrate and hence the base structure to vibrate and generate acoustic waves.
-
公开(公告)号:US20180331003A1
公开(公告)日:2018-11-15
申请号:US15776755
申请日:2015-12-16
Applicant: Intel Corporation
Inventor: Krishna BHARATH , Mathew J. MANUSHAROW , Adel A. ELSHERBINI , Mihir K. ROY , Aleksandar ALEKSOV , Yidnekachew S. MEKONNEN , Javier SOTO GONZALEZ , Feras EID , Suddhasattwa NAD , Meizi JIAO
IPC: H01L23/12 , H01L21/48 , H01L23/498
CPC classification number: H01L23/12 , H01L21/486 , H01L23/48 , H01L23/49822 , H01L23/49827 , H01L23/49838
Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.
-
公开(公告)号:US20180301405A1
公开(公告)日:2018-10-18
申请号:US15776402
申请日:2015-12-26
Applicant: Intel Corporation
Inventor: Robert L. SANKMAN , Adel A. ELSHERBINI
IPC: H01L23/498 , H01L23/538 , H01L23/00 , H01L25/065
CPC classification number: H01L23/49827 , H01L21/4857 , H01L21/486 , H01L23/147 , H01L23/49822 , H01L23/49833 , H01L23/5383 , H01L23/5385 , H01L24/19 , H01L24/20 , H01L25/0655 , H01L2224/16227 , H01L2224/16235 , H01L2224/73267
Abstract: Embodiments are generally directed to a conductive base embedded interconnect. An embodiment of an apparatus includes a substrate; an embedded interconnect layer in a first side of the substrate, the embedded interconnect layer including a plurality of contacts; and one or more conductive paths through the substrate, the one or more conductive paths being connected with the embedded interconnect layers.
-
公开(公告)号:US20180288868A1
公开(公告)日:2018-10-04
申请号:US15997644
申请日:2018-06-04
Applicant: Intel Corporation
Inventor: Adel A. ELSHERBINI , Matthew MANUSHAROW , Krishna BHARATH , Zhichao ZHANG , Yidnekachew S. MEKONNEN , Aleksandar ALEKSOV , Henning BRAUNISCH , Feras EID , Javier SOTO
Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
-
公开(公告)号:US20180003677A1
公开(公告)日:2018-01-04
申请号:US15199901
申请日:2016-06-30
Applicant: Intel Corporation
Inventor: Sasha N. OSTER , Feras EID , Georgios C. DOGIAMIS , Thomas L. SOUNART , Adel A. ELSHERBINI , Johanna M. SWAN , Shawna M. LIFF
IPC: G01N29/02 , B81B3/00 , G01N33/00 , G01N33/543 , G01N33/22 , G01N29/036
CPC classification number: G01N29/022 , B81B3/0021 , B81B2201/0214 , G01N29/036 , G01N29/2437 , G01N33/0047 , G01N33/227 , G01N33/54373 , G01N2291/0255 , G01N2291/0256 , G01N2291/0423
Abstract: Embodiments of the invention include a chemical species-sensitive device that includes an input transducer to receive input signals, a base structure that is coupled to the input transducer and positioned in proximity to a cavity of an organic substrate, a chemically sensitive functionalization material attached to the base structure, and an output transducer to generate output signals. For a chemical sensing functionality, a desired chemical species attaches to the chemically sensitive functionalization material which causes a change in mass of the base structure and this change in mass causes a change in a mechanical resonant frequency of the chemical species-sensitive device.
-
公开(公告)号:US20170288639A1
公开(公告)日:2017-10-05
申请号:US15088830
申请日:2016-04-01
Applicant: Intel Corporation
Inventor: Adel A. ELSHERBINI , Feras EID , Baris BICEN , Telesphor KAMGAING , Vijay K. NAIR , Georgios C. DOGIAMIS , Johanna M. SWAN , Valluri R. RAO
Abstract: Embodiments of the invention include a waveguide structure that includes a first piezoelectric transducer that is positioned in proximity to a first end of a cavity of an organic substrate. The first piezoelectric transducer receives an input electrical signal and generates an acoustic wave to be transmitted with a transmission medium. A second piezoelectric transducer is positioned in proximity to a second end of the cavity. The second piezoelectric transducer receives the acoustic wave from the transmission medium and generates an output electrical signal.
-
-
-
-
-
-
-
-
-