公开(公告)号：US20200006138A1

公开(公告)日：2020-01-02

申请号：US16024692

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Sudipto NASKAR ,  Manish CHANDHOK ,  Miriam RESHOTKO ,  Rami HOURANI

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

公开(公告)号：US20190214342A1

公开(公告)日：2019-07-11

申请号：US16329738

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Kevin LIN

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53295

Abstract: This disclosure is directed to systems and methods for maskless gap integration in interconnects having one or more vias above one or more interconnect lines (for example, metal interconnect lines). In various embodiments, the systems and methods described in the disclosure may serve to reduce electrical shorting between adjacent vias in the interconnects. In one embodiment, a spacer layer may be provided to mask portions of an interlayer dielectric (ILD) in the interconnect. These masked portions of the ILD can protect regions between adjacent interconnect lines from electrical shorting during subsequent metal layer depositions in a fabrication sequence of the interconnects. Further, in various embodiments, the vias may enclose a gap (for example, an air gap) without the need for additional masking steps, for example, without the need for additional lithography steps.

公开(公告)号：US20220238376A1

公开(公告)日：2022-07-28

申请号：US17720152

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Sudipto NASKAR ,  Manish CHANDHOK ,  Miriam RESHOTKO ,  Rami HOURANI

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L21/311 ,  H01L23/522 ,  H01L21/033

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

公开(公告)号：US20220157619A1

公开(公告)日：2022-05-19

申请号：US17592442

申请日：2022-02-03

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert Lindsey BRISTOL ,  Alan M. MYERS

IPC: H01L21/3213 ,  H01L21/768 ,  H01L21/033 ,  H01L23/522

Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.

公开(公告)号：US20220148917A1

公开(公告)日：2022-05-12

申请号：US17648821

申请日：2022-01-25

Applicant: Intel Corporation

Inventor： Carl NAYLOR ,  Ashish AGRAWAL ,  Kevin LIN ,  Abhishek Anil SHARMA ,  Mauro KOBRINSKY ,  Christopher JEZEWSKI ,  Urusa ALAAN

IPC: H01L21/768 ,  H01L21/683 ,  H01L23/532

Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.

公开(公告)号：US20190393298A1

公开(公告)日：2019-12-26

申请号：US16017964

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Han Wui THEN

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/66 ,  H01L27/07

Abstract: An integrated circuit structure comprises a first dielectric layer disposed above a substrate. The integrated circuit structure comprises an interconnect structure comprising a first interconnect on a first metal layer, a second interconnect on a second metal layer, and a via connecting the first interconnect and the second interconnect, the first interconnect being on or within the first dielectric layer. A metal-insulator-metal (MIM) capacitor is formed in or on the first dielectric layer in the first metal layer adjacent to the interconnect structure. The MIM capacitor comprises a bottom electrode plate comprising a first low resistivity material, an insulator stack on the bottom electrode plate, the insulator stack comprising at least one of an etch stop layer and a high-K dielectric layer; and a top electrode plate on the insulator stack, the top electrode plate comprising a second low resistivity material.

公开(公告)号：US20190385897A1

公开(公告)日：2019-12-19

申请号：US16463816

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： Manish CHANDHOK ,  Sudipto NASKAR ,  Stephanie A. BOJARSKI ,  Kevin LIN ,  Marie KRYSAK ,  Tristan A. TRONIC ,  Hui Jae YOO ,  Jeffery D. BIELEFELD ,  Jessica M. TORRES

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit die, a semiconductor structure, and a method of fabricating the semiconductor structure are disclosed. The integrated circuit die includes a substrate and a first anchor and a second anchor disposed on the substrate in a first plane. The integrated circuit die also includes a first wire disposed on the first anchor in the first plane, a third wire disposed on the second anchor in the first plane, and a second wire and a fourth wire suspended above the substrate in the first plane. The second wire is disposed between the first wire and the third wire and the third wire is disposed between the second wire and the fourth wire. The integrated circuit die further includes a dielectric material disposed between upper portions of the first wire, the second wire, the third wire, and the fourth wire to encapsulate an air gap.

公开(公告)号：US20190206733A1

公开(公告)日：2019-07-04

申请号：US16093076

申请日：2016-05-27

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert L. BRISTOL ,  Richard E. SCHENKER

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528

Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.

公开(公告)号：US20190164815A1

公开(公告)日：2019-05-30

申请号：US16092722

申请日：2016-05-27

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert L. BRISTOL ,  Richard E. SCHENKER

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/033

CPC classification number: H01L21/76816 ,  H01L21/0334 ,  H01L21/7682 ,  H01L21/76877 ,  H01L23/528

Abstract: Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.

公开(公告)号：US20210050261A1

公开(公告)日：2021-02-18

申请号：US17085882

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert L. BRISTOL ,  Richard E. SCHENKER

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.