公开(公告)号：US11709714B2

公开(公告)日：2023-07-25

申请号：US17686089

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Ben Ashbaugh ,  Jonathan Pearce ,  Murali Ramadoss ,  Vikranth Vemulapalli ,  William B. Sadler ,  Sungye Kim ,  Marian Alin Petre

IPC: G06F9/50 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0837 ,  G06F9/48 ,  G06F9/345 ,  G06T1/60 ,  G06F9/30 ,  G06T15/00 ,  G06F16/245 ,  G06T1/20

CPC classification number: G06F9/5027 ,  G06F9/3455 ,  G06F9/3851 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/4881 ,  G06F9/5033 ,  G06F9/5066 ,  G06F9/545 ,  G06F12/0837 ,  G06F9/30178 ,  G06F9/3887 ,  G06F16/24569 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005

Abstract: Embodiments are generally directed to thread group scheduling for graphics processing. An embodiment of an apparatus includes a plurality of processors including a plurality of graphics processors to process data; a memory; and one or more caches for storage of data for the plurality of graphics processors, wherein the one or more processors are to schedule a plurality of groups of threads for processing by the plurality of graphics processors, the scheduling of the plurality of groups of threads including the plurality of processors to apply a bias for scheduling the plurality of groups of threads according to a cache locality for the one or more caches.

公开(公告)号：US20220207656A1

公开(公告)日：2022-06-30

申请号：US17483074

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Anbang Yao ,  Ming Lu ,  Yikai Wang ,  Yurong Chen ,  Attila Tamas Afra ,  Sungye Kim ,  Karthik Vaidyanathan

IPC: G06T5/00 ,  G06N20/10 ,  G06N3/08

Abstract: Embodiments are generally directed to a Conditional Kernel Prediction Network (CKPN) for image and video de-noising and other related image and video processing applications. Disclosed is an embodiment of a method for de-noising an image or video frame by a convolutional neural network implemented on a compute engine, the image including a plurality of pixels, the method comprising: for each of the plurality of pixels of the image, generating a convolutional kernel having a plurality of kernel weights for the pixel, the plurality of kernel weights respectively corresponding to pixels within a region surrounding the pixel; adjusting the plurality of kernel weights of the convolutional kernel for the pixel based on convolutional kernels generated respectively for the corresponding pixels within the region surrounding the pixel; and filtering the pixel with the adjusted plurality of kernel weights and pixel values of the corresponding pixels within the region surrounding the pixel to obtain a de-noised pixel.

公开(公告)号：US20190236758A1

公开(公告)日：2019-08-01

申请号：US15883076

申请日：2018-01-29

Applicant: INTEL CORPORATION

Inventor： Sungye Kim ,  Seshupriya Alluru ,  Filip Strugar ,  Matthew Goyder ,  Yazdan Yar Khabiri ,  Anupreet Kalra ,  Kai Xiao

IPC: G06T5/00 ,  G06T15/04 ,  G06T15/40 ,  G06T7/13

CPC classification number: G06T5/002 ,  G06T7/13 ,  G06T15/04 ,  G06T15/405 ,  G06T2200/12 ,  G06T2207/20024 ,  G06T2207/20036 ,  G06T2207/20182

Abstract: Apparatus and method for temporally stable conservative morphological anti-aliasing. For example, one embodiment of a method comprises: rendering a current frame in a graphics processing apparatus, the current frame including color components and depth components; detecting edges within the rendered frame to generate a first set of edge candidates and a second set of edge candidates; performing spatial anti-aliasing using the first set of edge candidates; and performing temporal anti-aliasing using the second set of edge candidates.

公开(公告)号：US11416411B2

公开(公告)日：2022-08-16

申请号：US16354859

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Vikranth Vemulapalli ,  Niran Cooray ,  William B. Sadler ,  Jonathan D. Pearce ,  Marian Alin Petre ,  Ben Ashbaugh ,  Elmoustapha Ould-Ahmed-Vall ,  Nicolas Galoppo Von Borries ,  Altug Koker ,  Aravindh Anantaraman ,  Subramaniam Maiyuran ,  Varghese George ,  Sungye Kim ,  Valentin Andrei

IPC: G06F12/1009 ,  G06N20/00 ,  G06T1/20

Abstract: Methods and apparatus relating to predictive page fault handling. In an example, an apparatus comprises a processor to receive a virtual address that triggered a page fault for a compute process, check a virtual memory space for a virtual memory allocation for the compute process that triggered the page fault and manage the page fault according to one of a first protocol in response to a determination that the virtual address that triggered the page fault is a last page in the virtual memory allocation for the compute process, or a second protocol in response to a determination that the virtual address that triggered the page fault is not a last page in the virtual memory allocation for the compute process. Other embodiments are also disclosed and claimed.

公开(公告)号：US11409658B2

公开(公告)日：2022-08-09

申请号：US17161465

申请日：2021-01-28

Applicant: Intel Corporation

Inventor： Vikranth Vemulapalli ,  Lakshminarayanan Striramassarma ,  Mike MacPherson ,  Aravindh Anantaraman ,  Ben Ashbaugh ,  Murali Ramadoss ,  William B. Sadler ,  Jonathan Pearce ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter, Jr. ,  Prasoonkumar Surti ,  Nicolas Galoppo von Borries ,  Joydeep Ray ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Altug Koker ,  Sungye Kim ,  Subramaniam Maiyuran ,  Valentin Andrei

IPC: G09G5/36 ,  G06F12/0862 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

公开(公告)号：US20220207678A1

公开(公告)日：2022-06-30

申请号：US17482998

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Anbang Yao ,  Ming Lu ,  Yikai Wang ,  Shandong Wang ,  Yurong Chen ,  Sungye Kim ,  Attila Tamas Afra

IPC: G06T5/50 ,  G06K9/00 ,  G06T7/13 ,  G06N3/02

Abstract: The present disclosure provides an apparatus and method of guided neural network model for image processing. An apparatus may comprise a guidance map generator, a synthesis network and an accelerator. The guidance map generator may receive a first image as a content image and a second image as a style image, and generate a first plurality of guidance maps and a second plurality of guidance maps, respectively from the first image and the second image. The synthesis network may synthesize the first plurality of guidance maps and the second plurality of guidance maps to determine guidance information. The accelerator may generate an output image by applying the style of the second image to the first image based on the guidance information.

公开(公告)号：US10909039B2

公开(公告)日：2021-02-02

申请号：US16355015

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Vikranth Vemulapalli ,  Lakshminarayanan Striramassarma ,  Mike MacPherson ,  Aravindh Anantaraman ,  Ben Ashbaugh ,  Murali Ramadoss ,  William B. Sadler ,  Jonathan Pearce ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter, Jr. ,  Prasoonkumar Surti ,  Nicolas Galoppo von Borries ,  Joydeep Ray ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Altug Koker ,  Sungye Kim ,  Subramaniam Maiyuran ,  Valentin Andrei

IPC: G09G5/36 ,  G06F12/0862 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

公开(公告)号：US20200293450A1

公开(公告)日：2020-09-17

申请号：US16355015

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Vikranth Vemulapalli ,  Lakshminarayanan Striramassarma ,  Mike MacPherson ,  Aravindh Anantaraman ,  Ben Ashbaugh ,  Murali Ramadoss ,  William B. Sadler ,  Jonathan Pearce ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter, JR. ,  Prasoonkumar Surti ,  Nicolas Galoppo von Borries ,  Joydeep Ray ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Altug Koker ,  Sungye Kim ,  Subramaniam Maiyuran ,  Valentin Andrei

IPC: G06F12/0862 ,  G06T1/60 ,  G06T1/20

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

公开(公告)号：US20200293380A1

公开(公告)日：2020-09-17

申请号：US16355130

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Ben Ashbaugh ,  Jonathan Pearce ,  Murali Ramadoss ,  Vikranth Vemulapalli ,  William B. Sadler ,  Sungye Kim ,  Marian Alin Petre

IPC: G06F9/50 ,  G06F12/0837 ,  G06F9/38 ,  G06F9/54

Abstract: Embodiments are generally directed to thread group scheduling for graphics processing. An embodiment of an apparatus includes a plurality of processors including a plurality of graphics processors to process data; a memory; and one or more caches for storage of data for the plurality of graphics processors, wherein the one or more processors are to schedule a plurality of groups of threads for processing by the plurality of graphics processors, the scheduling of the plurality of groups of threads including the plurality of processors to apply a bias for scheduling the plurality of groups of threads according to a cache locality for the one or more caches.

公开(公告)号：US20250061172A1

公开(公告)日：2025-02-20

申请号：US18883195

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Anbang Yao ,  Ming Lu ,  Yikai Wang ,  Scott Janus ,  Sungye Kim

IPC: G06F18/2136 ,  G06T11/00

Abstract: Embodiments are generally directed to methods and apparatuses of spatially sparse convolution module for visual rendering and synthesis. An embodiment of a method for image processing, comprising: receiving an input image by a convolution layer of a neural network to generate a plurality of feature maps; performing spatially sparse convolution on the plurality of feature maps to generate spatially sparse feature maps; and upsampling the spatially sparse feature maps to generate an output image.