公开(公告)号：US11437483B2

公开(公告)日：2022-09-06

申请号：US16810156

申请日：2020-03-05

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Rahul Ramaswamy ,  Jeong Dong Kim ,  Babak Fallahazad ,  Hsu-Yu Chang ,  Ting Chang ,  Nidhi Nidhi ,  Walid M. Hafez

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

公开(公告)号：US10763209B2

公开(公告)日：2020-09-01

申请号：US15327338

申请日：2014-08-19

Applicant: INTEL CORPORATION

Inventor： Roman Olac-Vaw ,  Walid Hafez ,  Chia-Hong Jan ,  Hsu-Yu Chang ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu ,  Neville Dias

IPC: H01L29/78 ,  H01L23/525 ,  H01L29/423 ,  H01L29/66 ,  G11C17/16 ,  H01L21/768 ,  H01L27/112

Abstract: A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.

公开(公告)号：US09929090B2

公开(公告)日：2018-03-27

申请号：US15117621

申请日：2014-03-24

Applicant: INTEL CORPORATION

Inventor： Ting Chang ,  Chia-Hong Jan ,  Walid M. Hafez

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/62 ,  G11C17/14 ,  G11C17/16 ,  H01L27/112 ,  H01L27/102

CPC classification number: H01L23/5252 ,  G11C11/005 ,  G11C17/143 ,  G11C17/16 ,  G11C17/165 ,  H01L23/62 ,  H01L27/1021 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile memories. The memory circuitry employs an antifuse scheme that includes an array of 1 T bitcells, wherein each bitcell effectively contains one gate or transistor-like device that provides both an antifuse element and a selector device for that bitcell. In particular, the bitcell device has asymmetric trench-based source/drain contacts such that one contact forms a capacitor in conjunction with the spacer and gate metal, and the other contact forms a diode in conjunction with a doped diffusion area and the gate metal. The capacitor serves as the antifuse element of the bitcell, and can be programmed by breaking down the spacer. The diode effectively provides a Schottky junction that serves as a selector device which can eliminate program and read disturbs from bitcells sharing the same bitline/wordline.

公开(公告)号：US20170207312A1

公开(公告)日：2017-07-20

申请号：US15327641

申请日：2014-08-19

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid Hafez ,  Hsu-Yu Chang ,  Roman Olac-Vaw ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu ,  Neville Dias

IPC: H01L29/423 ,  H01L23/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/535

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823475 ,  H01L23/535 ,  H01L23/66 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/78

Abstract: Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.

公开(公告)号：US12040395B2

公开(公告)日：2024-07-16

申请号：US16713648

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Ting Chang ,  Babak Fallahazad ,  Tanuj Trivedi ,  Jeong Dong Kim

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7816 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66704 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78696

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a substrate, a source region over the substrate, a drain region over the substrate, and a semiconductor body extending from the source region to the drain region. In an embodiment, the semiconductor body has a first region with a first conductivity type and a second region with a second conductivity type. In an embodiment, the semiconductor device further comprises a gate structure over the first region of the semiconductor body, where the gate structure is closer to the source region than the drain region.

公开(公告)号：US11862703B2

公开(公告)日：2024-01-02

申请号：US17870401

申请日：2022-07-21

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Rahul Ramaswamy ,  Jeong Dong Kim ,  Babak Fallahazad ,  Hsu-Yu Chang ,  Ting Chang ,  Nidhi Nidhi ,  Walid M. Hafez

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/42392 ,  H01L21/02532 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1062 ,  H01L29/165 ,  H01L29/66795

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

公开(公告)号：US11581404B2

公开(公告)日：2023-02-14

申请号：US17308900

申请日：2021-05-05

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Jeong Dong Kim ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Rahul Ramaswamy ,  Ting Chang ,  Babak Fallahazad

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/285

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

公开(公告)号：US09799668B2

公开(公告)日：2017-10-24

申请号：US14779938

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Ting Chang ,  Chia-Hong Jan ,  Walid M. Hafez

IPC: H01L27/115 ,  H01L27/11563 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11563 ,  G11C16/0475 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: Memory cells having isolated charge sites and methods of fabricating memory cells having isolated charge sites are described. In an example, a nonvolatile charge trap memory device includes a substrate having a channel region, a source region and a drain region. A gate stack is disposed above the substrate, over the channel region. The gate stack includes a tunnel dielectric layer disposed above the channel region, a first charge-trapping region and a second charge-trapping region. The regions are disposed above the tunnel dielectric layer and separated by a distance. The gate stack also includes an isolating dielectric layer disposed above the tunnel dielectric layer and between the first charge-trapping region and the second charge-trapping region. A gate dielectric layer is disposed above the first charge-trapping region, the second charge-trapping region and the isolating dielectric layer. A gate electrode is disposed above the gate dielectric layer.