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    ARCHITECTURE AND INSTRUCTION SET FOR IMPLEMENTING ADVANCED ENCRYPTION STANDARD (AES)
    12.
    发明申请
    ARCHITECTURE AND INSTRUCTION SET FOR IMPLEMENTING ADVANCED ENCRYPTION STANDARD (AES) 审中-公开
    实施高级加密标准（AES）的架构和指导

    公开(公告)号：US20160119122A1

    公开(公告)日：2016-04-28

    申请号：US14947944

    申请日：2015-11-20

    Applicant: INTEL CORPORATION

    Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

    IPC: H04L9/06 ,  H04L9/14

    Abstract: A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.

    Abstract translation: 提供了一种用于通用处理器的灵活的aes指令，其使用n次循环执行aes加密或解密，其中n包括标准的一组轮{10,12,14}。 提供了一个参数，以允许选择一轮的类型，即是否是“最后一轮”。 除了标准aes之外，灵活的aes指令允许指定具有20发的AES类密码或“一轮”通过。

    SMS4 ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    14.
    发明申请
    SMS4 ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 有权
    SMS4加速处理器，方法，系统和指令

    公开(公告)号：US20150186138A1

    公开(公告)日：2015-07-02

    申请号：US14142724

    申请日：2013-12-27

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: G06F9/30 ,  G06F21/60

    CPC classification number: G06F9/30145 ,  G06F9/30007 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3895 ,  G06F21/602 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/125

    Abstract: A processor of an aspect includes a plurality of packed data registers and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SMS4 rounds. The one or more source operands are also to have a 32-bit value. An execution unit is coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store a 32-bit result of a current SMS4 round in a destination storage location that is to be indicated by the instruction.

    Abstract translation: 一方面的处理器包括多个打包数据寄存器和用于解码指令的解码单元。 该指令是指示一个或多个源打包数据操作数。 一个或多个源打包数据操作数具有四个先前的SMS4回合的四个32位结果。 一个或多个源操作数也具有32位值。 执行单元与解码单元和多个打包数据寄存器耦合。 执行单元响应于该指令，将当前SMS4的32位结果存储在要由指令指示的目的地存储单元中。

    INSTRUCTIONS AND LOGIC TO PROVIDE SIMD SM4 CRYPTOGRAPHIC BLOCK CIPHER FUNCTIONALITY
    19.
    发明申请
    INSTRUCTIONS AND LOGIC TO PROVIDE SIMD SM4 CRYPTOGRAPHIC BLOCK CIPHER FUNCTIONALITY 有权

    公开(公告)号：US20220353070A1

    公开(公告)日：2022-11-03

    申请号：US17718237

    申请日：2022-04-11

    Applicant: Intel Corporation

    Inventor： Sean M. Gulley ,  Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: H04L9/08 ,  H04L9/06 ,  G06F21/72 ,  G06F9/30 ,  G09C1/00 ,  G06F9/38

    Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

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