公开(公告)号：US11531542B2

公开(公告)日：2022-12-20

申请号：US17393361

申请日：2021-08-03

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Matthew C. Merten ,  Tong Li ,  Bret L. Toll

IPC: G06F9/30 ,  G06F9/38

Abstract: A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

公开(公告)号：US10725779B2

公开(公告)日：2020-07-28

申请号：US16450319

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Kirk S. Yap ,  Gilbert M. Wolrich ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC: G06F9/30 ,  G06F21/60 ,  G06F12/0875 ,  G06F12/1027 ,  G09C1/00 ,  H04L9/32 ,  G06F9/38 ,  G06F12/0897 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42 ,  G06F15/80 ,  H04L9/06

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US10594475B2

公开(公告)日：2020-03-17

申请号：US15639983

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

IPC: G06F21/00 ,  H04L9/06 ,  G06F9/30 ,  G06F21/60 ,  H04L9/14

Abstract: A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.

公开(公告)号：US10198248B2

公开(公告)日：2019-02-05

申请号：US13631761

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Sean M. Gulley ,  Wajdi K. Feghali ,  Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Kirk S. Yap

IPC: G06F5/06 ,  G06F21/64 ,  H04L9/06 ,  H04L9/32

Abstract: Technologies for executing a serial data processing algorithm on a single variable length data buffer includes streaming segments of the buffer into a data register, executing the algorithm on each of the segments in parallel, and combining the results of executing the algorithm on each of the segments to form the output of the serial data processing algorithm.

公开(公告)号：US20170310470A1

公开(公告)日：2017-10-26

申请号：US15639991

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

IPC: H04L9/06 ,  G06F21/60 ,  H04L9/14

Abstract: A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.

公开(公告)号：US09654281B2

公开(公告)日：2017-05-16

申请号：US14572593

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G. Dixon ,  Srinivas Chennupaty ,  Michael E. Kounavis

IPC: H04L9/28 ,  G06F21/72 ,  H04L9/06 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

CPC classification number: H04L9/0631 ,  G06F3/0623 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3887 ,  G06F9/3895 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/602 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/602 ,  G11C7/1072 ,  H04L9/0816 ,  H04L9/0861 ,  H04L2209/12 ,  H04L2209/24

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US09634829B2

公开(公告)日：2017-04-25

申请号：US14572565

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G. Dixon ,  Srinivas Chennupaty ,  Michael E. Kounavis

IPC: H04L9/06 ,  H04L9/28 ,  H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G11C7/10 ,  G06F3/06

CPC classification number: H04L9/0631 ,  G06F3/0623 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3887 ,  G06F9/3895 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/602 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/602 ,  G11C7/1072 ,  H04L9/0816 ,  H04L9/0861 ,  H04L2209/12 ,  H04L2209/24

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US09495165B2

公开(公告)日：2016-11-15

申请号：US14556931

申请日：2014-12-01

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Erdinc Ozturk ,  Wajdi K. Feghali ,  Gilbert M. Wolrich ,  Martin G. Dixon

IPC: G06F7/00 ,  G06F7/38 ,  G06F1/02 ,  G06F17/50 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3893

Abstract: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

公开(公告)号：US20160248580A1

公开(公告)日：2016-08-25

申请号：US14984616

申请日：2015-12-30

Applicant: Intel Corporation

Inventor： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G. Dixon ,  Srinivas Chennupaty ,  Michael E. Kounavis

IPC: H04L9/06 ,  G06F9/38 ,  G06F3/06 ,  G11C7/10 ,  G06F12/08

CPC classification number: H04L9/0631 ,  G06F3/0623 ,  G06F3/0665 ,  G06F3/0689 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3887 ,  G06F9/3895 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/602 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/602 ,  G11C7/1072 ,  H04L9/0816 ,  H04L9/0861 ,  H04L2209/12 ,  H04L2209/24

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

公开(公告)号：US20160119126A1

公开(公告)日：2016-04-28

申请号：US14984637

申请日：2015-12-30

Applicant: Intel Corporation

Inventor： Gueron Shay ,  Wajdi K. Feghali ,  Vinodh Gopal ,  Raghunandan Makaram ,  Martin G. Dixon ,  Srinivas Chennupaty ,  Michael E. Kounavis

IPC: H04L9/06 ,  G06F12/08 ,  G06F12/14

Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.