Method for manufacturing an electronic device

    公开(公告)号:US12148658B2

    公开(公告)日:2024-11-19

    申请号:US18074525

    申请日:2022-12-05

    Abstract: The present disclosure discloses a method for manufacturing an electronic device, including: setting a basic working area; a photoresist coating process; a development process; an etching process; an exposure process; a metal plating process; and a polishing process, wherein the photoresist coating process, the development process, the etching process, the exposure process, the metal plating process and the polishing process respectively have a maximum optimized process area, and a smallest one of the maximum optimized process areas is selected as the basic working area.

    Electronic component and manufacturing method thereof

    公开(公告)号:US12142554B2

    公开(公告)日:2024-11-12

    申请号:US17523895

    申请日:2021-11-10

    Abstract: An electronic component and a manufacturing method thereof are provided. The electronic component includes a structure member and a connecting member. The structure member includes at least one working unit. The at least one working unit is disposed in a first region. The connecting member is disposed on the structure member and includes a second region. The second region is overlapped with the first region, and a metal density of the second region is less than a metal density of the first region. The electronic component and the manufacturing method thereof of the embodiment of the disclosure include the effect of improving the reliability or quality of the electronic component.

    Package device and manufacturing method thereof

    公开(公告)号:US11812549B2

    公开(公告)日:2023-11-07

    申请号:US18094995

    申请日:2023-01-10

    CPC classification number: H05K1/0269 H05K3/022 H05K3/46

    Abstract: A package device and a manufacturing method thereof are provided. The package device includes a redistribution layer. The redistribution layer includes a first dielectric layer, a conductive layer, and a second dielectric layer, and the conductive layer is disposed between the first dielectric layer and the second dielectric layer, wherein the redistribution layer has a test mark, the test mark includes a conductive pattern formed of the conductive layer, the conductive pattern includes a center portion and a plurality of extension portions, and the plurality of extension portions are respectively connected to the center portion.

    MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE

    公开(公告)号:US20220181189A1

    公开(公告)日:2022-06-09

    申请号:US17520599

    申请日:2021-11-05

    Abstract: A manufacturing method of a semiconductor package is provided. The manufacturing method includes the following. A plurality of semiconductor components are provided. Each semiconductor component has at least one conductive bump. A substrate is provided. The substrate has a plurality of conductive pads. A transfer device is provided. The transfer device transfers the semiconductor components onto the substrate. A heating device is provided. The heating device heats or pressurizes at least two semiconductor components. During transferring of the semiconductor components to the substrate, the at least one conductive bump of each semiconductor component is docked to a corresponding one of the conductive pads.

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