公开(公告)号：US20210109839A1

公开(公告)日：2021-04-15

申请号：US17128291

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Adarsh Chauhan ,  Jayesh Gaur ,  Franck Sala ,  Lihu Rappoport ,  Zeev Sperber ,  Adi Yoaz ,  Sreenivas Subramoney

IPC: G06F11/34 ,  G06F11/30 ,  G06F9/24 ,  G06F9/38 ,  G06F15/78

Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

公开(公告)号：US20190243684A1

公开(公告)日：2019-08-08

申请号：US15890984

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： Pooja Roy ,  Jayesh Gaur ,  Sreenivas Subramoney ,  Zeev Sperber ,  Alexandr Titov ,  Lihu Rappoport ,  Stanislav Shwartsman ,  Hong Wang ,  Adi Yoaz ,  Ronak Singhal ,  Robert S. Chappell

IPC: G06F9/48 ,  G06F9/38

Abstract: A processor including an execution unit, an instruction scheduler circuit to identify a first instruction of an instruction stream, identify a second instruction on which execution of the first instruction depends, and assign a first dispatch priority value to the first instruction and the second instruction, and a dispatch circuit to dispatch, based on the first dispatch priority value, the first instruction and the second instruction to an instruction execution circuit.