公开(公告)号：US20180137053A1

公开(公告)日：2018-05-17

申请号：US15352272

申请日：2016-11-15

Applicant: INTEL CORPORATION

Inventor： Pavel I. Kryukov ,  Stanislav Shwartsman ,  Joseph Nuzman ,  Alexandr Titov

IPC: G06F12/0808 ,  G06F12/0811 ,  G06F12/0837 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891

CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0837 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/502 ,  G06F2212/6042

Abstract: An example system on a chip (SoC) includes a cache, a processor, and a predictor circuit. The cache may store data. The processor may be coupled to the cache and store a first data set at a first location in the cache and receive a first request from an application to write a second data set to the cache. The predictor circuit may be coupled to the processor and determine that a second location where the second data set is to be written to in the cache is nonconsecutive to the first location, where the processor is to perform a request-for-ownership (RFO) operation for the second data set and write the second data set to the cache.

公开(公告)号：US20180285119A1

公开(公告)日：2018-10-04

申请号：US15562408

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Alexandr Titov ,  Dmitry Maslennikov ,  Sergey Y. SHISHLOV ,  Valentin Burov ,  Pavel Matveyev

IPC: G06F9/38

Abstract: A processor includes execution units, a front end, and an execution engine. The front end includes logic to receive instructions in different strands of ordered instructions and to send the instructions to the execution engine. The engine includes logic to determine that the instructions in different strands reference a same logical register mapped to a physical register, that the instructions reference each other, and that one of the instructions referencing the other was processed after the instruction defining the logical register.

公开(公告)号：US10719355B2

公开(公告)日：2020-07-21

申请号：US15890984

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： Pooja Roy ,  Jayesh Gaur ,  Sreenivas Subramoney ,  Zeev Sperber ,  Alexandr Titov ,  Lihu Rappoport ,  Stanislav Shwartsman ,  Hong Wang ,  Adi Yoaz ,  Ronak Singhal ,  Robert S. Chappell

IPC: G06F9/48 ,  G06F9/38

Abstract: A processor including an execution unit, an instruction scheduler circuit to identify a first instruction of an instruction stream, identify a second instruction on which execution of the first instruction depends, and assign a first dispatch priority value to the first instruction and the second instruction, and a dispatch circuit to dispatch, based on the first dispatch priority value, the first instruction and the second instruction to an instruction execution circuit.

公开(公告)号：US10133669B2

公开(公告)日：2018-11-20

申请号：US15352272

申请日：2016-11-15

Applicant: INTEL CORPORATION

Inventor： Pavel I. Kryukov ,  Stanislav Shwartsman ,  Joseph Nuzman ,  Alexandr Titov

IPC: G06F12/08 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0837 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891

Abstract: An example system on a chip (SoC) includes a cache, a processor, and a predictor circuit. The cache may store data. The processor may be coupled to the cache and store a first data set at a first location in the cache and receive a first request from an application to write a second data set to the cache. The predictor circuit may be coupled to the processor and determine that a second location where the second data set is to be written to in the cache is nonconsecutive to the first location, where the processor is to perform a request-for-ownership (RFO) operation for the second data set and write the second data set to the cache.

公开(公告)号：US20190243684A1

公开(公告)日：2019-08-08

申请号：US15890984

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： Pooja Roy ,  Jayesh Gaur ,  Sreenivas Subramoney ,  Zeev Sperber ,  Alexandr Titov ,  Lihu Rappoport ,  Stanislav Shwartsman ,  Hong Wang ,  Adi Yoaz ,  Ronak Singhal ,  Robert S. Chappell

IPC: G06F9/48 ,  G06F9/38

Abstract: A processor including an execution unit, an instruction scheduler circuit to identify a first instruction of an instruction stream, identify a second instruction on which execution of the first instruction depends, and assign a first dispatch priority value to the first instruction and the second instruction, and a dispatch circuit to dispatch, based on the first dispatch priority value, the first instruction and the second instruction to an instruction execution circuit.