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1.发明授权公开(公告)号：US11645078B2
公开(公告)日：2023-05-09
申请号：US16729349
申请日：2019-12-28
Applicant: Intel Corporation
Inventor： Adarsh Chauhan , Franck Sala , Jayesh Gaur , Zeev Sperber , Lihu Rappoport , Adi Yoaz , Sreenivas Subramoney
CPC classification number: G06F9/3806 , G06F9/30058 , G06F9/30145
Abstract: Systems, methods, and apparatuses relating to hardware for auto-predication of critical branches. In one embodiment, a processor core includes a decoder to decode instructions into decoded instructions, an execution unit to execute the decoded instructions, a branch predictor circuit to predict a future outcome of a branch instruction, and a branch predication manager circuit to disable use of the predicted future outcome for a conditional critical branch comprising the branch instruction.
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公开(公告)号：US11256599B2
公开(公告)日：2022-02-22
申请号：US17128291
申请日：2020-12-21
Applicant: Intel Corporation
Inventor： Adarsh Chauhan , Jayesh Gaur , Franck Sala , Lihu Rappoport , Zeev Sperber , Adi Yoaz , Sreenivas Subramoney
Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.
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公开(公告)号：US11656971B2
公开(公告)日：2023-05-23
申请号：US17582051
申请日：2022-01-24
Applicant: Intel Corporation
Inventor： Adarsh Chauhan , Jayesh Gaur , Franck Sala , Lihu Rappoport , Zeev Sperber , Adi Yoaz , Sreenivas Subramoney
CPC classification number: G06F11/3476 , G06F9/24 , G06F9/3836 , G06F11/3024 , G06F11/3055 , G06F15/7875
Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.
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公开(公告)号：US20220206925A1
公开(公告)日：2022-06-30
申请号：US17582051
申请日：2022-01-24
Applicant: Intel Corporation
Inventor： Adarsh Chauhan , Jayesh Gaur , Franck Sala , Lihu Rappoport , Zeev Sperber , Adi Yoaz , Sreenivas Subramoney
Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.
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公开(公告)号：US10915421B1
公开(公告)日：2021-02-09
申请号：US16575535
申请日：2019-09-19
Applicant: Intel Corporation
Inventor： Adarsh Chauhan , Jayesh Gaur , Franck Sala , Lihu Rappoport , Zeev Sperber , Adi Yoaz , Sreenivas Subramoney
Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US10467011B2
公开(公告)日：2019-11-05
申请号：US14336596
申请日：2014-07-21
Applicant: Intel Corporation
Inventor： Lihu Rappoport , Zeev Sperber , Michael Mishaeli , Stanislav Shwartsman , Lev Makovsky , Adi Yoaz , Ofer Levy
Abstract: A processor of an aspect includes a decode unit to decode a thread pause instruction from a first thread. A back-end portion of the processor is coupled with the decode unit. The back-end portion of the processor, in response to the thread pause instruction, is to pause processing of subsequent instructions of the first thread for execution. The subsequent instructions occur after the thread pause instruction in program order. The back-end portion, in response to the thread pause instruction, is also to keep at least a majority of the back-end portion of the processor, empty of instructions of the first thread, except for the thread pause instruction, for a predetermined period of time. The majority may include a plurality of execution units and an instruction queue unit.
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公开(公告)号：US20160019063A1
公开(公告)日：2016-01-21
申请号：US14336596
申请日：2014-07-21
Applicant: Intel Corporation
Inventor： Lihu Rappoport , Zeev Sperber , Michael Mishaeli , Stanislav Shwartsman , Lev Makovsky , Adi Yoaz , Ofer Levy
IPC: G06F9/30
CPC classification number: G06F9/3851 , G06F9/30 , G06F9/30058 , G06F9/3009
Abstract: A processor of an aspect includes a decode unit to decode a thread pause instruction from a first thread. A back-end portion of the processor is coupled with the decode unit. The back-end portion of the processor, in response to the thread pause instruction, is to pause processing of subsequent instructions of the first thread for execution. The subsequent instructions occur after the thread pause instruction in program order. The back-end portion, in response to the thread pause instruction, is also to keep at least a majority of the back-end portion of the processor, empty of instructions of the first thread, except for the thread pause instruction, for a predetermined period of time. The majority may include a plurality of execution units and an instruction queue unit.
Abstract translation: 一个方面的处理器包括解码单元，用于对来自第一线程的线程暂停指令进行解码。 处理器的后端部分与解码单元耦合。 响应于线程暂停指令，处理器的后端部分是暂停用于执行的第一线程的后续指令的处理。 随后的指令以程序顺序发生在线程暂停指令之后。 响应于线程暂停指令，后端部分还将保持处理器的后端部分的至少大部分，除了线程暂停指令之外的第一线程的指令，预定的 一段的时间。 大多数可以包括多个执行单元和指令队列单元。
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公开(公告)号：US10754655B2
公开(公告)日：2020-08-25
申请号：US16021838
申请日：2018-06-28
Applicant: Intel Corporation
Inventor： Adarsh Chauhan , Hong Wang , Jayesh Gaur , Zeev Sperber , Sumeet Bandishte , Lihu Rappoport , Stanislav Shwartsman , Kamil Garifullin , Sreenivas Subramoney , Adi Yoaz
Abstract: A processing device includes a branch IP table and branch predication circuitry coupled to the branch IP table. The branch predication circuitry to: determine a dynamic convergence point in a conditional branch of set of instructions; store the dynamic convergence point in the branch IP table; fetch a first and second speculative path of the conditional branch; while determining which of the first speculative path and the second speculative path is a taken path of the conditional branch and determining whether a dynamic convergence point is fetched corresponding to the stored dynamic convergence point, stall scheduling of instructions of the first speculative path and the second speculative path; and in response to determining that one of the first speculative path and the second speculative path is the taken path and the fetched dynamic convergence point corresponds to the stored convergence point, resume scheduling of the instructions of the taken path.
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公开(公告)号：US10719355B2
公开(公告)日：2020-07-21
申请号：US15890984
申请日：2018-02-07
Applicant: Intel Corporation
Inventor： Pooja Roy , Jayesh Gaur , Sreenivas Subramoney , Zeev Sperber , Alexandr Titov , Lihu Rappoport , Stanislav Shwartsman , Hong Wang , Adi Yoaz , Ronak Singhal , Robert S. Chappell
Abstract: A processor including an execution unit, an instruction scheduler circuit to identify a first instruction of an instruction stream, identify a second instruction on which execution of the first instruction depends, and assign a first dispatch priority value to the first instruction and the second instruction, and a dispatch circuit to dispatch, based on the first dispatch priority value, the first instruction and the second instruction to an instruction execution circuit.
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公开(公告)号：US20200004542A1
公开(公告)日：2020-01-02
申请号：US16021838
申请日：2018-06-28
Applicant: Intel Corporation
Inventor： Adarsh Chauhan , Jayesh Gaur , Zeev Sperber , Sumeet Bandishte , Lihu Rappoport , Stanislav Shwartsman , Kamil Garifullin , Sreenivas Subramoney , Adi Yoaz , Hong Wang
Abstract: A processing device includes a branch IP table and branch predication circuitry coupled to the branch IP table. The branch predication circuitry to: determine a dynamic convergence point in a conditional branch of set of instructions; store the dynamic convergence point in the branch IP table; fetch a first and second speculative path of the conditional branch; while determining which of the first speculative path and the second speculative path is a taken path of the conditional branch and determining whether a dynamic convergence point is fetched corresponding to the stored dynamic convergence point, stall scheduling of instructions of the first speculative path and the second speculative path; and in response to determining that one of the first speculative path and the second speculative path is the taken path and the fetched dynamic convergence point corresponds to the stored convergence point, resume scheduling of the instructions of the taken path.
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