公开(公告)号：US20200075567A1

公开(公告)日：2020-03-05

申请号：US16119837

申请日：2018-08-31

Applicant: Intel Corporation

Inventor： Andrew Collins

IPC: H01L25/18 ,  H01L23/13 ,  H01L23/538 ,  H01L23/00 ,  G11C29/04 ,  H01L23/48 ,  H01L23/367 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

Abstract: A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.

公开(公告)号：US20190304911A1

公开(公告)日：2019-10-03

申请号：US15937411

申请日：2018-03-27

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Debendra Mallik ,  Mathew J. Manusharow ,  Jianyong Xie

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/48

Abstract: An embedded multi-die interconnect bridge (EMIB) die is configured with power delivery to the center of the EMIB die and the power is distributed to two dice that are interconnected across the EMIB die.

公开(公告)号：US12205924B2

公开(公告)日：2025-01-21

申请号：US18112430

申请日：2023-02-21

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Jianyong Xie

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528

Abstract: Apparatuses, devices and systems associated with semiconductor packages with chiplet and memory device coupling are disclosed herein. In embodiments, a semiconductor package may include a first chiplet, a second chiplet, and a memory device. The semiconductor package may further include an interconnect structure that couples the first chiplet to a first memory channel of the memory device and the second chiplet to a second memory channel of the memory device. Other embodiments may be described and/or claimed.

公开(公告)号：US12051647B2

公开(公告)日：2024-07-30

申请号：US18199735

申请日：2023-05-19

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Bharat P. Penmecha ,  Rajasekaran Swaminathan ,  Ram Viswanath

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5283 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/17 ,  H01L24/23 ,  H01L25/0655 ,  H01L25/18

Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

公开(公告)号：US11705398B2

公开(公告)日：2023-07-18

申请号：US17585082

申请日：2022-01-26

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Bharat P. Penmecha ,  Rajasekaran Swaminathan ,  Ram Viswanath

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5283 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/17 ,  H01L24/23 ,  H01L25/0655 ,  H01L25/18

Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

公开(公告)号：US11456281B2

公开(公告)日：2022-09-27

申请号：US16147742

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Yí Li ,  Zhiguo Qian ,  Prasad Ramanathan ,  Saikumar Jayaraman ,  Kemal Aygun ,  Hector Amador ,  Andrew Collins ,  Jianyong Xie ,  Shigeki Tomishima

IPC: H01L25/065 ,  H01L25/10 ,  H01L25/00

Abstract: Embodiments include electronic packages and methods of forming such packages. An electronic package includes a memory module comprising a first memory die. The first memory die includes first interconnects with a first pad pitch and second interconnects with a second pad pitch, where the second pad pitch is less than the first pad pitch. The memory module also includes a redistribution layer below the first memory die, and a second memory die below the redistribution layer, where the second memory die has first interconnects with a first pad pitch and second interconnects with a second pad pitch. The memory module further includes a mold encapsulating the second memory die, where through mold interconnects (TMIs) provide an electrical connection from the redistribution layer to mold layer. The TMIs may be through mold vias. The TMIs may be made through a passive interposer that is encapsulated in the mold.

公开(公告)号：US11018124B2

公开(公告)日：2021-05-25

申请号：US16119837

申请日：2018-08-31

Applicant: Intel Corporation

Inventor： Andrew Collins

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/00 ,  G11C29/04 ,  H01L23/48 ,  H01L23/367 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/13

Abstract: A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.

公开(公告)号：US20190393142A1

公开(公告)日：2019-12-26

申请号：US16015739

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Jianyong Xie ,  Sujit Sharan

IPC: H01L23/498 ,  H01L25/16 ,  H01L49/02 ,  H01L23/42 ,  H01L21/48

Abstract: A micro-trace containing package substrate provides a low-inductance alternating-current decoupling path between a semiconductive device and a die-side capacitor.

公开(公告)号：US12046568B2

公开(公告)日：2024-07-23

申请号：US18214742

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Sujit Sharan ,  Jianyong Xie

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L25/00 ,  H01L25/16 ,  H01L23/48

CPC classification number: H01L23/66 ,  H01L21/4846 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/5381 ,  H01L23/5389 ,  H01L25/16 ,  H01L25/50 ,  H01L23/481 ,  H01L2223/6666 ,  H01L2223/6672

Abstract: A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

公开(公告)号：US11728294B2

公开(公告)日：2023-08-15

申请号：US17518504

申请日：2021-11-03

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Sujit Sharan ,  Jianyong Xie

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/538 ,  H01L23/528 ,  H01L25/00 ,  H01L21/48 ,  H01L25/16 ,  H01L23/48

CPC classification number: H01L23/66 ,  H01L21/4846 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/5381 ,  H01L23/5389 ,  H01L25/16 ,  H01L25/50 ,  H01L23/481 ,  H01L2223/6666 ,  H01L2223/6672

Abstract: A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.