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公开(公告)号：US10706004B2
公开(公告)日：2020-07-07
申请号：US15811848
申请日：2017-11-14
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Guy G. Sotomayor , Andrew D. Henroid , Robert E. Gough , Tod F. Schiff
Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.
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公开(公告)号：US09766673B2
公开(公告)日：2017-09-19
申请号：US14633438
申请日：2015-02-27
Applicant: Intel Corporation
Inventor： Ankush Varma , Vasudevan Srinivasan , Eugene Gorbatov , Andrew D. Henroid , Barnes Cooper , David W. Browning , Guy M. Therien , Neil W. Songer , Krishnakanth V. Sistla , James G. Hermerding, II
CPC classification number: G06F1/263 , G06F1/206 , G06F1/3212 , G06F1/324 , G06F15/00 , Y02D10/126 , Y02D10/16 , Y02D10/174
Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.
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公开(公告)号：US20170003724A1
公开(公告)日：2017-01-05
申请号：US15262816
申请日：2016-09-12
Applicant: Intel Corporation
Inventor： Guy M. Therien , Paul S. Diefenbaugh , Anil Aggarwal , Andrew D. Henroid , Jeremy J. Shrall , Efraim Rotem , Krishnakanth V. Sistla , Eliezer Weissmann
CPC classification number: G06F9/4403 , G06F1/206 , G06F1/26 , G06F1/28 , G06F1/32 , G06F1/3203 , G06F1/3234 , G06F1/324 , G06F1/3275 , G06F1/3296 , G06F9/22 , G06F9/30098 , G06F9/3012 , G06F9/384 , G06F9/44 , G06F9/4401 , G06F9/4418 , G06F9/445 , G06F11/3024 , G06F11/3409 , G06F11/3447 , G06F11/3466 , G06F11/3664 , G06F11/3672 , G06F11/3688 , G06F15/7871 , G06F17/30339 , G06F2209/501 , G06F2217/78 , Y02D10/126 , Y02D10/172
Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
Abstract translation: 本发明涉及一种平台电源管理方案。 在一些实施例中，平台使用OSPM系统请求的一个或多个参数来提供相对性能量表。
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公开(公告)号：US09110735B2
公开(公告)日：2015-08-18
申请号：US13728327
申请日：2012-12-27
Applicant: Intel Corporation
Inventor： Paul S. Diefenbaugh , Andrew D. Henroid , Eliezer Weissmann , Krishnakanth V. Sistla
IPC: G06F1/00 , G06F9/46 , G06F15/173 , G06F9/50 , G06F1/32
CPC classification number: G06F9/5094 , G06F1/3203 , Y02D10/22
Abstract: Methods and systems may provide for identifying a workload associated with a platform and determining a scalability of the workload. Additionally, a performance policy of the platform may be managed based at least in part on the scalability of the workload. In one example, determining the scalability includes determining a ratio of productive cycles to actual cycles.
Abstract translation: 方法和系统可以提供用于识别与平台相关联的工作负载并确定工作负载的可扩展性。 此外，可以至少部分地基于工作负载的可扩展性来管理平台的性能策略。 在一个示例中，确定可伸缩性包括确定生产周期与实际周期的比率。
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公开(公告)号：US11221857B2
公开(公告)日：2022-01-11
申请号：US16388670
申请日：2019-04-18
Applicant: Intel Corporation
Inventor： Guy M. Therien , Paul S. Diefenbaugh , Anil Aggarwal , Andrew D. Henroid , Jeremy J. Shrall , Efraim Rotem , Krishnakanth V. Sistla , Eliezer Weissmann
IPC: G06F1/00 , G06F11/30 , G06F9/4401 , G06F16/22 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F9/44 , G06F9/445 , G06F1/28 , G06F1/3234 , G06F11/36 , G06F1/26 , G06F9/22 , G06F11/34 , G06F9/30 , G06F1/20 , G06F15/78 , G06F1/32 , G06F9/38 , G06F119/06
Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
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Patent Agency Ranking
公开(公告)号：US10275260B2
公开(公告)日：2019-04-30
申请号：US15262816
申请日：2016-09-12
Applicant: Intel Corporation
Inventor： Guy M. Therien , Paul S. Diefenbaugh , Anil Aggarwal , Andrew D. Henroid , Jeremy J. Shrall , Efraim Rotem , Krishnakanth V. Sistla , Eliezer Weissmann
IPC: G06F1/00 , G06F11/30 , G06F9/4401 , G06F17/30 , G06F9/44 , G06F9/445 , G06F1/28 , G06F1/3234 , G06F11/36 , G06F1/26 , G06F9/22 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F11/34 , G06F9/30 , G06F1/20 , G06F15/78 , G06F1/32 , G06F9/38
Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
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公开(公告)号：US10162687B2
公开(公告)日：2018-12-25
申请号：US13730800
申请日：2012-12-28
Applicant: Intel Corporation
Inventor： Eugene Gorbatov , Alon Naveh , Inder M. Sodhi , Ganapati N. Srinivasa , Eliezer Weissmann , Guarav Khanna , Mishali Naik , Russell J. Fenger , Andrew D. Henroid , Dheeraj R. Subbareddy , David A. Koufaty , Paolo Narvaez
Abstract: A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.
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公开(公告)号：US10007528B2
公开(公告)日：2018-06-26
申请号：US13683748
申请日：2012-11-21
Applicant: Intel Corporation
Inventor： Guy M. Therien , Paul Diefenbaugh , Anil Aggarwal , Andrew D. Henroid , Jeremy J. Shrall , Efraim Rotem , Krishnakanth V. Sistla , Eliezer Weissmann , Mohan Kumar , Sarathy Jayakumar , Jose Andy Vargas , Neelam Chandwani , Michael A. Rothman , Robert Gough , Mark Doran
IPC: G06F17/30 , G06F9/4401 , G06F9/44 , G06F9/445 , G06F1/28 , G06F11/36 , G06F1/26 , G06F9/22 , G06F11/30 , G06F11/34 , G06F9/30 , G06F1/20 , G06F15/78 , G06F1/32 , G06F9/38
CPC classification number: G06F9/4403 , G06F1/206 , G06F1/26 , G06F1/28 , G06F1/32 , G06F1/3203 , G06F1/3234 , G06F1/324 , G06F1/3275 , G06F1/3296 , G06F9/22 , G06F9/30098 , G06F9/3012 , G06F9/384 , G06F9/44 , G06F9/4401 , G06F9/4418 , G06F9/445 , G06F11/3024 , G06F11/3409 , G06F11/3447 , G06F11/3466 , G06F11/3664 , G06F11/3672 , G06F11/3688 , G06F15/7871 , G06F16/2282 , G06F2209/501 , G06F2217/78 , Y02D10/126 , Y02D10/172
Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.
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公开(公告)号：US20180067892A1
公开(公告)日：2018-03-08
申请号：US15811848
申请日：2017-11-14
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth V. Sistla , Guy G. Sotomayor , Andrew D. Henroid , Robert E. Gough , Tod F. Schiff
CPC classification number: G06F15/00 , G06F1/206 , G06F1/26 , G06F1/3243 , G06F9/45541 , G06F9/45558 , G06F9/5077 , G06F9/5094 , G06F2009/4557 , Y02D10/152 , Y02D10/16
Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.
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公开(公告)号：US09727345B2
公开(公告)日：2017-08-08
申请号：US13854001
申请日：2013-03-29
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russell J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
CPC classification number: G06F9/4401 , G06F9/45558 , G06F9/5077 , G06F9/5094 , Y02D10/22 , Y02D10/36
Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
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