公开(公告)号：US11990419B2

公开(公告)日：2024-05-21

申请号：US16905202

申请日：2020-06-18

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Feras Eid ,  Adel Elsherbini ,  David Johnston ,  Jyothi Bhaskarr Velamala ,  Rachael Parker

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/498 ,  H04L9/32

CPC classification number: H01L23/544 ,  H01L23/49838 ,  H01L24/73 ,  H04L9/3278 ,  H01L2223/54413 ,  H01L2224/73204

Abstract: Techniques and mechanisms for providing physically unclonable function (PUF) circuitry at a substrate which supports coupling to an integrated circuit (IC) chip. In an embodiment, the substrate comprises an array of electrodes which extend in a level of metallization at a side of the insulator layer. A cap layer, disposed on the array, is in contact with the electrodes and with a portion of the insulator layer which is between the electrodes. A material of the cap layer has a different composition or microstructure than the metallization. Regions of the cap layer variously provide respective impedances each between a corresponding two electrodes. In other embodiments, the substrate includes (or couples to) integrated circuitry that is operable to determine security information based on the detection of one or more such impedances.

公开(公告)号：US11720672B2

公开(公告)日：2023-08-08

申请号：US17728907

申请日：2022-04-25

Applicant: Intel Corporation

Inventor： Kuan-Yueh Shen ,  David Johnston ,  Rachael J. Parker ,  Javier Dacuna Santos

IPC: G06F11/00 ,  G06F21/55 ,  G06F11/10 ,  H04L9/32 ,  H04L9/08 ,  G06F7/58 ,  G06F21/00

CPC classification number: G06F21/556 ,  G06F7/588 ,  G06F11/1076 ,  G06F21/00 ,  H04L9/0866 ,  H04L9/0894 ,  H04L9/3278 ,  G06F2221/034 ,  H04L2209/34

Abstract: The disclosure generally provides methods, systems and apparatus for an improved a Physically Unclonable Function (PUF). In one embodiment, the disclosure relates to a method to provide data from a Physically Unclonable Function (PUF) circuit array. The method includes storing a plurality of first data bits into a respective ones of a plurality of first bitcells of the PUF array to form a first dataset; storing a plurality of second data bits into a respective ones of a plurality of second bitcells of the PUF array, the plurality of second data bits defining a helper dataset; reading the first dataset from the plurality of first bitcells to provide a first read dataset; applying an error correction factor to the first read data dataset to form a security key dataset; and outputting the security key dataset from the PUF circuit array.

公开(公告)号：US11196709B2

公开(公告)日：2021-12-07

申请号：US15927338

申请日：2018-03-21

Applicant: Intel Corporation

Inventor： Farid Adrangi ,  David Johnston

IPC: H04L29/12 ,  H04L12/721 ,  H04L12/741 ,  H04W12/02 ,  H04L29/06 ,  H04L9/08 ,  H04W12/06 ,  H04W84/12

Abstract: This disclosure describes systems, methods, and apparatus related to receiving, at an access point and from a wireless communication station, a media access control (MAC) address of the wireless communication station; assigning, at the access point, a prefix to the MAC address of the wireless communication station; receiving, at the access point and from the wireless communication station, a frame comprising the prefix and a random MAC address; replacing, at the access point and using the prefix, the random MAC address in the frame with the MAC address of the wireless communication station, thereby resulting in a processed frame; and transmitting, at the access point and to a destination device, the processed frame.

公开(公告)号：US20190130103A1

公开(公告)日：2019-05-02

申请号：US16234348

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Kuan-Yueh Shen ,  David Johnston ,  Rachael J. Parker ,  Javier Dacuna Santos

IPC: G06F21/55 ,  G06F11/10 ,  H04L9/08

Abstract: The disclosure generally provides methods, systems and apparatus for an improved a Physically Unclonable Function (PUF). In one embodiment, the disclosure relates to a method to provide data from a Physically Unclonable Function (PUF) circuit array. The method includes storing a plurality of first data bits into a respective ones of a plurality of first bitcells of the PUF array to form a first dataset; storing a plurality of second data bits into a respective ones of a plurality of second bitcells of the PUF array, the plurality of second data bits defining a helper dataset; reading the first dataset from the plurality of first bitcells to provide a fist read dataset; applying an error correction factor to the first read data dataset to form a security key dataset; and outputting the security key dataset from the PUF circuit array.

公开(公告)号：US09992031B2

公开(公告)日：2018-06-05

申请号：US14040337

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Kevin Gotze ,  Gregory Iovino ,  David Johnston ,  Patrick Koeberl ,  Jiangtao Li ,  Wei Wu

IPC: H04L9/34 ,  H04L9/08 ,  H04L9/32 ,  G09C1/00

CPC classification number: H04L9/34 ,  G09C1/00 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

Abstract: Embodiments of an invention for using dark bits to reduce physically unclonable function (PUF) error rates are disclosed. In one embodiment, an integrated circuit includes a PUF cell array and dark bit logic. The PUF cell array is to provide a raw PUF value. The dark bit logic is to select PUF cells to mark as dark bits and to generate a dark bit mask based on repeated testing of the PUF cell array.

公开(公告)号：US11567733B2

公开(公告)日：2023-01-31

申请号：US16849103

申请日：2020-04-15

Applicant: Intel Corporation

Inventor： Yee Hui Lee ,  Boon Hong Oh ,  David Johnston ,  David Wheeler

IPC: G06F7/58 ,  G06F15/78

Abstract: The disclosure relates to systems, methods and devices to provide race-condition true random number generator (TRNG) for soft intellectual property (IP) in field-programmable gate arrays (FPGAs). In an exemplary embodiment, a pair of long adder chains are raced against one another to complete a full cycle. Due to variances in the silicon, different chains will win each race at different times and thereby produce entropy. A calibration circuit can be used to set up the adder chains in an appropriate initial state to maximize the entropy produced. This structure has been found to be robust to layout changes, and the use of two such adder-chain-pairs reduces interference from other structures. Among others, the soft IP makes adding a robust TRNG to an FPGA much easier without concerns for how the structures are laid out or what other IP is nearby in the layout. The disclosed embodiments reduces the effort to add a TRNG to an FPGA design and improves the robustness of the TRNG making the design FIPS certifiable.

公开(公告)号：US11321459B2

公开(公告)日：2022-05-03

申请号：US16234348

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Kuan-Yueh Shen ,  David Johnston ,  Rachael J. Parker ,  Javier Dacuna Santos

IPC: G06F11/00 ,  G06F21/55 ,  G06F11/10 ,  H04L9/32 ,  H04L9/08 ,  G06F7/58 ,  G06F21/00

Abstract: The disclosure generally provides methods, systems and apparatus for an improved a Physically Unclonable Function (PUF). In one embodiment, the disclosure relates to a method to provide data from a Physically Unclonable Function (PUF) circuit array. The method includes storing a plurality of first data bits into a respective ones of a plurality of first bitcells of the PUF array to form a first dataset; storing a plurality of second data bits into a respective ones of a plurality of second bitcells of the PUF array, the plurality of second data bits defining a helper dataset; reading the first dataset from the plurality of first bitcells to provide a first read dataset; applying an error correction factor to the first read data dataset to form a security key dataset; and outputting the security key dataset from the PUF circuit array.

公开(公告)号：US20220100475A1

公开(公告)日：2022-03-31

申请号：US17541247

申请日：2021-12-03

Applicant: Intel Corporation

Inventor： Yee Hui Lee ,  Boon Hong Oh ,  David Johnston ,  David Wheeler

IPC: G06F7/58 ,  G06F15/78

Abstract: The disclosure relates to systems, methods and devices to provide race-condition true random number generator (TRNG) for soft intellectual property (IP) in field-programmable gate arrays (FPGAs). In an exemplary embodiment, a pair of long adder chains are raced against one another to complete a full cycle. Due to variances in the silicon, different chains will win each race at different times and thereby produce entropy. A calibration circuit can be used to set up the adder chains in an appropriate initial state to maximize the entropy produced. This structure has been found to be robust to layout changes, and the use of two such adder-chain-pairs reduces interference from other structures. Among others, the soft IP makes adding a robust TRNG to an FPGA much easier without concerns for how the structures are laid out or what other IP is nearby in the layout. The disclosed embodiments reduces the effort to add a TRNG to an FPGA design and improves the robustness of the TRNG making the design FIPS certifiable.

公开(公告)号：US10015014B2

公开(公告)日：2018-07-03

申请号：US14583701

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： David Johnston ,  David W. Grawrock

IPC: H04L29/06 ,  H04L9/32 ,  G09C1/00

CPC classification number: H04L9/3242 ,  G09C1/00 ,  H04L9/3271

Abstract: Technologies for secure presence assurance include a computing device having a presence assertion circuitry that receives an input seed value and generates a cryptographic hash based on the received input seed value. The computing device further verifies the integrity of the presence assertion circuitry based on the generated cryptographic hash.

公开(公告)号：US20170090872A1

公开(公告)日：2017-03-30

申请号：US14865009

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Sanu K. Mathew ,  David Johnston ,  Sudhir K. Satpathy

IPC: G06F7/58

CPC classification number: G06F7/588 ,  G06F7/483 ,  G06F2207/58 ,  H04L9/0637 ,  H04L9/0869

Abstract: A processor includes an execution unit to generate a random number. The execution unit includes entropy source circuits, correlation circuits, and an extractor circuit. The entropy source circuits include all-digital components and are to generate an initial randomized bit stream. The correlation circuits are to remove correlations from the initial randomized bit stream to yield an intermediate randomized bit stream. The extractor circuit is to select a subset of the intermediate randomized bit stream as a random output of the execution unit.