公开(公告)号：US20230197678A1

公开(公告)日：2023-06-22

申请号：US17558265

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Mohammad Enamul Kabir ,  Debendra Mallik

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0657 ,  H01L2924/15311

Abstract: A microelectronic package structure with inorganic fill material having a first die with a second and an adjacent third die on the first die. Each of the second and third die comprise hybrid bonding interfaces with the first die. A first layer is on a region of the first die between the second and third dies. A second layer is over the first layer, the second layer comprising an inorganic dielectric material, wherein a top surface of the second layer is substantially coplanar with top surfaces of the second and third dies.

公开(公告)号：US11658111B2

公开(公告)日：2023-05-23

申请号：US17200700

申请日：2021-03-12

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Poh Boon Khoo ,  Eng Huat Goh ,  Amruthavalli Pallavi Alur ,  Debendra Mallik

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L24/09 ,  H01L24/17 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2924/01029

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

公开(公告)号：US20230080454A1

公开(公告)日：2023-03-16

申请号：US17473694

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Brandon C. Marin ,  Debendra Mallik ,  Tarek A. Ibrahim ,  Jeremy Ecton ,  Omkar G. Karhade ,  Bharat Prasad Penmecha ,  Xiaoqian Li ,  Nitin A. Deshpande ,  Mitul Modi ,  Bai Nie

IPC: G02B6/12 ,  H01L23/48

Abstract: An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

公开(公告)号：US20220404553A1

公开(公告)日：2022-12-22

申请号：US17354446

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Ankur Agrawal ,  Benjamin Duong ,  Ravindranath Mahajan ,  Debendra Mallik ,  Srinivas Pietambaram

IPC: G02B6/26

Abstract: An integrated circuit package may be formed comprising a first integrated circuit assembly, a second integrated circuit assembly, and a means to transfer optical signals therebetween. This optical signal transfer may be facilitated with a first lens or a first micro-lens array adjacent at least one waveguide of the first integrated circuit assembly and a second lens or second micro-lens array adjacent at least one waveguide of the second integrated circuit assembly, wherein the optical signals are transmitted across a gap between the first lens/micro-lens array and the second lens/micro-lens array. In further embodiments, the optical signal transfer assembly may comprise at least one photonic bridge between at least one waveguide of the first integrated circuit assembly and at least one waveguide of the second integrated circuit assembly.

公开(公告)号：US20210035881A1

公开(公告)日：2021-02-04

申请号：US16529617

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Ravindranath Mahajan ,  Digvijay Raorane

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

公开(公告)号：US10910317B2

公开(公告)日：2021-02-02

申请号：US16461316

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Vipul Vijay Mehta ,  Eric Jin Li ,  Sanka Ganesan ,  Debendra Mallik ,  Robert Leon Sankman

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/14 ,  H01L21/768

Abstract: Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.

公开(公告)号：US20200273768A1

公开(公告)日：2020-08-27

申请号：US16287668

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Kumar Singh

IPC: H01L23/31 ,  H01L23/532 ,  H01L23/34 ,  H01L23/00 ,  H01L21/56

Abstract: IC packages including a heat spreading material comprising crystalline carbon. The heat spreading material may be applied directly to an IC die surface, for example at a die prep stage, prior to an application or build-up of packaging material, so that the high thermal conductivity may best mitigate any hot spots that develop at the IC die surface during operation. The heat spreading material may be applied to surface of the IC die.

公开(公告)号：US10366951B2

公开(公告)日：2019-07-30

申请号：US15620555

申请日：2017-06-12

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L23/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20180350737A1

公开(公告)日：2018-12-06

申请号：US16002740

申请日：2018-06-07

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18 ,  H01L21/56

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US10074357B2

公开(公告)日：2018-09-11

申请号：US14877602

申请日：2015-10-07

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Kelin J. Kuhn ,  Debendra Mallik ,  John C. Johnson

IPC: G01K11/32 ,  G10K11/34

CPC classification number: G10K11/346 ,  A41D2400/00 ,  H04R1/403 ,  H04R1/406 ,  H04R2201/023 ,  H04R2201/401 ,  H04R2499/11 ,  H04R2499/15

Abstract: A system includes a processor and a phased array, coupled to the processor, having an arrayed waveguide for acoustic waves to enable directional sound communication.