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    Interface Bus for Inter-Die Communication in a Multi-Chip Package Over High Density Interconnects
    11.
    发明申请
    Interface Bus for Inter-Die Communication in a Multi-Chip Package Over High Density Interconnects 审中-公开

    公开(公告)号：US20190042505A1

    公开(公告)日：2019-02-07

    申请号：US16023724

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  MD Altaf Hossain

    IPC: G06F13/38 ,  G06F13/42 ,  H01L23/00 ,  H01L25/065

    Abstract: An IC includes first, second, and third IOs, and a multiplexer that includes first and second inputs, and an output. The IC includes first and second transmitters respectively having an output coupled to the first IO and an output coupled to the second IO. A clock generator is coupled between the output and an input of the first transmitter and between the output and an input of the second transmitter. The first input may receive a clock signal generated by the first clock generator and the second clock input is coupled to the third IO and may receive a clock signal via the third IO element from another IC. An IC includes a programmable fabric, k*n wires coupled to and extending from the fabric, n TDMs, and n IO blocks. Each TDM includes k inputs coupled to k wires and an output coupled to one of the IO blocks.

    Innovative interconnect design for package architecture to improve latency
    12.
    发明授权
    Innovative interconnect design for package architecture to improve latency 有权

    公开(公告)号：US12266625B2

    公开(公告)日：2025-04-01

    申请号：US18599147

    申请日：2024-03-07

    Applicant: Intel Corporation

    Inventor： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

    IPC: G06F13/38 ,  G06F13/14 ,  G06F13/42 ,  H01L23/00 ,  H01L25/065

    Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

    SEGMENTED ROW REPAIR FOR PROGRAMMABLE LOGIC DEVICES
    17.
    发明申请
    SEGMENTED ROW REPAIR FOR PROGRAMMABLE LOGIC DEVICES 有权

    公开(公告)号：US20220113350A1

    公开(公告)日：2022-04-14

    申请号：US17559322

    申请日：2021-12-22

    Applicant: Intel Corporation

    Inventor： Dheeraj Subbareddy ,  Arun Jangity ,  Ramya Yeluri ,  Mahesh K. Kumashikar ,  Atul Maheshwari ,  Ankireddy Nalamalpu

    IPC: G01R31/3177

    Abstract: Systems or methods of the present disclosure may provide a programmable logic device including multiple logic array blocks each having multiple programmable elements. The multiple logic array blocks are arranged in multiple rows that are segmented into multiple segments. The programmable logic device also includes repair circuitry disposed between the multiple segments. The repair circuitry remaps logic within a first segment of the multiple segments when a first logic array block of the multiple logic array blocks has failed. Moreover, the first segment includes the first logic array block.

    Innovative Interconnect Design for Package Architecture to Improve Latency
    18.
    发明申请
    Innovative Interconnect Design for Package Architecture to Improve Latency 有权

    公开(公告)号：US20220059491A1

    公开(公告)日：2022-02-24

    申请号：US17466396

    申请日：2021-09-03

    Applicant: Intel Corporation

    Inventor： MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

    IPC: H01L23/00 ,  G06F13/38 ,  H01L25/065 ,  G06F13/42 ,  G06F13/14

    Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

    Interface Bus for Inter-Die Communication in a Multi-Chip Package Over High Density Interconnects
    19.
    发明申请
    Interface Bus for Inter-Die Communication in a Multi-Chip Package Over High Density Interconnects 有权

    公开(公告)号：US20210288013A1

    公开(公告)日：2021-09-16

    申请号：US17335012

    申请日：2021-05-31

    Applicant: Intel Corporation

    Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  MD Altaf Hossain

    IPC: H01L23/00 ,  G06F13/38 ,  H01L25/065 ,  G06F13/42 ,  G06F13/14

    Abstract: An IC includes first, second, and third IOs, and a multiplexer that includes first and second inputs, and an output. The IC includes first and second transmitters respectively having an output coupled to the first IO and an output coupled to the second IO. A clock generator is coupled between the output and an input of the first transmitter and between the output and an input of the second transmitter. The first input may receive a clock signal generated by the first clock generator and the second clock input is coupled to the third IO and may receive a clock signal via the third IO element from another IC. An IC includes a programmable fabric, k*n wires coupled to and extending from the fabric, n TDMs, and n IO blocks. Each TDM includes k inputs coupled to k wires and an output coupled to one of the IO blocks.

    Innovative interconnect design for package architecture to improve latency
    20.
    发明授权
    Innovative interconnect design for package architecture to improve latency 有权

    公开(公告)号：US11121109B2

    公开(公告)日：2021-09-14

    申请号：US16023846

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

    IPC: G06F13/38 ,  H01L23/00 ,  H01L25/065 ,  G06F13/42 ,  G06F13/14

    Abstract: An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.

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