公开(公告)号：US20230259412A1

公开(公告)日：2023-08-17

申请号：US18136972

申请日：2023-04-20

Applicant: Intel Corporation

Inventor： Haokun Xing ,  Miaomiao Liu ,  Hualong Feng ,  Ziye Yang ,  Junyuan Wang

IPC: G06F9/54

CPC classification number: G06F9/541 ,  G06F9/547

Abstract: Various methods, systems, and use cases for providing a wrapper application programming interface (API). The wrapper API can invoke hardware accelerator libraries based on function calls from cloud native applications.

公开(公告)号：US11687375B2

公开(公告)日：2023-06-27

申请号：US17724764

申请日：2022-04-20

Applicant: Intel Corporation

Inventor： Ned Smith ,  Changzheng Wei ,  Songwu Shen ,  Ziye Yang ,  Junyuan Wang ,  Weigang Li ,  Wenqian Yu

IPC: G06F9/50 ,  G06F21/76 ,  G06F21/60

CPC classification number: G06F9/5044 ,  G06F9/505 ,  G06F21/76 ,  G06F21/602 ,  G06F2209/509 ,  Y02D10/00

Abstract: Technologies for hybrid field-programmable gate array (FPGA) application-specific integrated circuit (ASIC) code acceleration are described. In one example, the computing device includes a FPGA comprising: algorithm circuitry to: perform one or more algorithm tasks of an algorithm, wherein the algorithm to perform a service request that is offloaded to the FPGA; and determine a primitive task associated with an algorithm task of the one or more algorithm tasks; primitive offload circuitry to encapsulate the primitive task in a buffer of the FPGA, wherein the buffer is accessible by an ASIC of the computing device; and result circuitry to return one or more results of the service request responsive to performance of the primitive task by the ASIC.

公开(公告)号：US20230195201A1

公开(公告)日：2023-06-22

申请号：US18110603

申请日：2023-02-16

Applicant: Intel Corporation

Inventor： Junyuan Wang ,  Timothy Waite ,  Ziye Yang ,  Hu Chen ,  Zixuan Li ,  Anna Czarnowska ,  Olayinka Olubayo ,  Gordon McFadden

IPC: G06F1/324 ,  G06F9/50

CPC classification number: G06F1/324 ,  G06F9/5094

Abstract: An accelerator apparatus can include an interface to receive service requests from at least one processing core. The accelerator apparatus can include coprocessor circuitry coupled to the interface and comprised of multiple slices. The coprocessor circuitry can detect a performance type for the at least one processing core. The coprocessor circuitry can operate the plurality of coprocessor slices in at least one of a plurality of power modes based on the performance type detected for the at least one processing core. Some operations can be alternatively performed by an operating system on any processor coupled to the network.

公开(公告)号：US20210326182A1

公开(公告)日：2021-10-21

申请号：US17220763

申请日：2021-04-01

Applicant: Intel Corporation

Inventor： Ned M. Smith ,  Changzheng Wei ,  Songwu Shen ,  Ziye Yang ,  Junyuan Wang ,  Weigang Li ,  Wenqian Yu

IPC: G06F9/50 ,  G06F21/76

Abstract: Technologies for hybrid acceleration of code include a computing device (100) having a processor (120), a field-programmable gate array (FPGA) (130), and an application-specific integrated circuit (ASIC) (132). The computing device (100) offloads a service request, such as a cryptographic request or a packet processing request, to the FPGA (130). The FPGA (130) performs one or more algorithmic tasks of an algorithm to perform the service request. The FPGA (130) determines one or more primitive tasks associated with an algorithm task and encapsulates each primitive task in a buffer that is accessible by the ASIC (132). The ASIC (132) performs the primitive tasks in response to encapsulation in the buffer, and the FPGA (130) returns results of the algorithm. The primitive operations may include cryptographic primitives such as modular exponentiation, modular multiplicative inverse, and modular multiplication. The results may be returned to the processor (120) or a network interface controller of the computing device (100).

公开(公告)号：US10970119B2

公开(公告)日：2021-04-06

申请号：US15755216

申请日：2017-03-28

Applicant: INTEL CORPORATION

Inventor： Ned M. Smith ,  Changzheng Wei ,  Songwu Shen ,  Ziye Yang ,  Junyuan Wang ,  Weigang Li ,  Wenqian Yu

IPC: G06F9/50 ,  G06F21/76 ,  G06F21/60

Abstract: Technologies for hybrid acceleration of code include a computing device (100) having a processor (120), a field-programmable gate array (FPGA) (130), and an application-specific integrated circuit (ASIC) (132). The computing device (100) offloads a service request, such as a cryptographic request or a packet processing request, to the FPGA (130). The FPGA (130) performs one or more algorithmic tasks of an algorithm to perform the service request. The FPGA (130) determines one or more primitive tasks associated with an algorithm task and encapsulates each primitive task in a buffer that is accessible by the ASIC (132). The ASIC (132) performs the primitive tasks in response to encapsulation in the buffer, and the FPGA (130) returns results of the algorithm. The primitive operations may include cryptographic primitives such as modular exponentiation, modular multiplicative inverse, and modular multiplication. The results may be returned to the processor (120) or a network interface controller of the computing device (100).

公开(公告)号：US20250110903A1

公开(公告)日：2025-04-03

申请号：US18978180

申请日：2024-12-12

Applicant: Intel Corporation

Inventor： Dongsheng Liang ,  Junyuan Wang ,  Xiaoyan Bo ,  Yuze Xiao ,  Haoxiang Sun ,  Weigang Li ,  Marian Horgan ,  Fei Wang ,  John J. Browne ,  Laurent Coquerel ,  Giovanni Cabiddu ,  Vijay Sundar Selvamani ,  Steven Linsell ,  Karthikeyan Gopal ,  Deepika Ranganatha

IPC: G06F13/28

Abstract: A hardware accelerator device is provided with accelerator hardware to perform dictionary compressions in hardware based on a request from an application executed by a processor device coupled to the hardware accelerator device to compress data for the application.

公开(公告)号：US20230216849A1

公开(公告)日：2023-07-06

申请号：US18008743

申请日：2021-07-07

Applicant: Intel Corporation

Inventor： Ned M. Smith ,  Junyuan Wang ,  Kaijie Guo ,  Zijuan Fan ,  Weigang Li ,  Lihui Zhang

IPC: H04L9/40

CPC classification number: H04L63/0884 ,  H04L63/20

Abstract: Various examples of device and system implementations and methods for performing attestation delegation operations are disclosed. In an example, attestation operations are performed by a verifier, including: obtaining endorsement information for attestation of an entity; obtaining an appraisal policy for evaluation of attestation evidence for the attestation of the entity; determining, based on the endorsement information and the appraisal policy, that delegation to a delegate verifier entity is permitted to perform the attestation of the entity; and providing, to the delegate verifier entity, a delegation command to perform the attestation of the entity, wherein the delegation command authorizes the delegate verifier entity to perform attestation operations (e.g., verifier operations) for a domain of entities including the entity.

公开(公告)号：US20220244999A1

公开(公告)日：2022-08-04

申请号：US17724764

申请日：2022-04-20

Applicant: Intel Corporation

Inventor： Ned Smith ,  Changzheng Wei ,  Songwu Shen ,  Ziye Yang ,  Junyuan Wang ,  Weigang Li ,  Wenqian Yu

IPC: G06F9/50 ,  G06F21/76

Abstract: Technologies for hybrid field-programmable gate array (FPGA) application-specific integrated circuit (ASIC) code acceleration are described. In one example, the computing device includes a FPGA comprising: algorithm circuitry to: perform one or more algorithm tasks of an algorithm, wherein the algorithm to perform a service request that is offloaded to the FPGA; and determine a primitive task associated with an algorithm task of the one or more algorithm tasks; primitive offload circuitry to encapsulate the primitive task in a buffer of the FPGA, wherein the buffer is accessible by an ASIC of the computing device; and result circuitry to return one or more results of the service request responsive to performance of the primitive task by the ASIC.

公开(公告)号：US20200371953A1

公开(公告)日：2020-11-26

申请号：US16989667

申请日：2020-08-10

Applicant: Intel Corporation

Inventor： Kaijie Guo ,  Weigang Li ,  Junyuan Wang ,  Liang Ma ,  Maksim Lukoshkov ,  Yao Huo

IPC: G06F12/1009 ,  H04L29/12 ,  G06F12/1027 ,  G06F13/42 ,  G06F13/28

Abstract: Examples herein relate to a system that includes a first memory device; a second memory device; and an input-output memory management unit (IOMMU). The IOMMU can search for a virtual-to-physical address translation entry in a first table for a received virtual address and based on a virtual-to-physical address translation entry for the received virtual address not being present in the first table, search a second table for a virtual-to-physical address translation entry for the received virtual address, wherein the first table is stored in the first memory device and the second table is stored in the second memory device. In some examples, based on a virtual-to-physical address translation entry for the received virtual address not being present in the second table, a page table walk is performed to determine a virtual-to-physical address translation for the received virtual address. In some examples, the first table includes an IO translation lookaside buffer (IOTLB).