公开(公告)号：US09977075B1

公开(公告)日：2018-05-22

申请号：US15360899

申请日：2016-11-23

Applicant: Intel Corporation

Inventor： Christopher F. Connor ,  Bruce Querbach ,  Gordon McFadden ,  Rahul Khanna

IPC: G06Q10/06 ,  G06Q10/08 ,  G01R31/28 ,  G06F17/50

CPC classification number: G01R31/2851 ,  G01R31/2855 ,  G06F17/5036

Abstract: Embodiments detailed herein include an apparatus that includes a reliability assessment engine (RAE) stored in non-volatile memory and processing circuitry to execute the RAE to: receive data of at least one physical condition from a plurality of intra-die variation monitoring circuits, apply the received data least one to at least one reliability physics model, and calculate at least one of an estimated amount of lifetime consumed and an estimated amount of lifetime remaining.

公开(公告)号：US20170160338A1

公开(公告)日：2017-06-08

申请号：US14961824

申请日：2015-12-07

Applicant: Intel Corporation

Inventor： Christopher F. Connor ,  Bruce Querbach ,  Gordon McFadden ,  Hanmant P. Belgal ,  Rahul Khanna

IPC: G01R31/28 ,  G11C29/00 ,  G11C7/00

CPC classification number: G01R31/2894 ,  G11C5/04 ,  G11C7/00 ,  G11C16/3495 ,  G11C29/025 ,  G11C29/16 ,  G11C29/40 ,  G11C29/50016 ,  G11C2029/5004

Abstract: In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that include a reliability physics module stored in non-volatile memory and compute logic to calculate at least one of an estimated amount of lifetime consumed or an estimated amount of lifetime remaining after a period of operation of an integrated circuit. In embodiments, the calculation may be based at least in part on the reliability physics model and data of at least one physical condition of the integrated circuit sensed during or at the end of the period of operation. Other embodiments may be described and/or claimed.

公开(公告)号：US20230195201A1

公开(公告)日：2023-06-22

申请号：US18110603

申请日：2023-02-16

Applicant: Intel Corporation

Inventor： Junyuan Wang ,  Timothy Waite ,  Ziye Yang ,  Hu Chen ,  Zixuan Li ,  Anna Czarnowska ,  Olayinka Olubayo ,  Gordon McFadden

IPC: G06F1/324 ,  G06F9/50

CPC classification number: G06F1/324 ,  G06F9/5094

Abstract: An accelerator apparatus can include an interface to receive service requests from at least one processing core. The accelerator apparatus can include coprocessor circuitry coupled to the interface and comprised of multiple slices. The coprocessor circuitry can detect a performance type for the at least one processing core. The coprocessor circuitry can operate the plurality of coprocessor slices in at least one of a plurality of power modes based on the performance type detected for the at least one processing core. Some operations can be alternatively performed by an operating system on any processor coupled to the network.

公开(公告)号：US09612930B2

公开(公告)日：2017-04-04

申请号：US14737768

申请日：2015-06-12

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Eric Rasmussen ,  Deep K. Buch ,  Gordon McFadden ,  Kameswar Subramaniam ,  Amy L. Santoni ,  Willard M. Wiseman ,  Bret L. Toll

IPC: G06F11/00 ,  G06F11/263 ,  G06F11/22 ,  G06F11/14

CPC classification number: G06F11/2635 ,  G06F11/1417 ,  G06F11/1433 ,  G06F11/2242 ,  G06F11/2268 ,  G06F11/27

Abstract: In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.

公开(公告)号：US20180143242A1

公开(公告)日：2018-05-24

申请号：US15360899

申请日：2016-11-23

Applicant: Intel Corporation

Inventor： Christopher F. Connor ,  Bruce Querbach ,  Gordon McFadden ,  Rahul Khanna

IPC: G01R31/28 ,  G06F17/50

CPC classification number: G01R31/2851 ,  G01R31/2855 ,  G06F17/5036

Abstract: Embodiments detailed herein include an apparatus that includes a reliability assessment engine (RAE) stored in non-volatile memory and processing circuitry to execute the RAE to: receive data of at least one physical condition from a plurality of intra-die variation monitoring circuits, apply the received data least one to at least one reliability physics model, and calculate at least one of an estimated amount of lifetime consumed and an estimated amount of lifetime remaining.

公开(公告)号：US20180095802A1

公开(公告)日：2018-04-05

申请号：US15283006

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Hang T. Nguyen ,  Gordon McFadden ,  Pradeepsunder Ganesh ,  Stephen Thomas Palermo ,  Travis J. White ,  Ashok Raj ,  Vivek Garg ,  Dhruv Singh

IPC: G06F9/50

CPC classification number: G06F9/5044 ,  G06F9/5094 ,  Y02D10/22

Abstract: In one embodiment, a method comprises determining, at a plurality of instances in time, a value of at least one stress characteristic of a hardware resource; determining an accumulated stress value of the hardware resource, the accumulated stress value comprising the sum of a plurality of incremental stress values, an incremental stress value determined based on the value of the at least one stress characteristic at a particular instance in time; and generating a first stress indicator in response to a determination that the accumulated stress value of the hardware resource is greater than a first threshold stress value associated with the hardware resource.

公开(公告)号：US20160378628A1

公开(公告)日：2016-12-29

申请号：US14752821

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Hang T. Nguyen ,  Gordon McFadden ,  Travis J. White ,  Scott P. Bobholz ,  Edwin Verplanke ,  Steven C. Franks ,  Vivek Garg ,  Ashok Raj ,  Guy G. Sotomayor ,  Jose A. Vargas ,  Pradeepsunder Ganesh ,  Stephen T. Palermo

IPC: G06F11/273 ,  G06F11/22

CPC classification number: G06F11/2236 ,  G06F11/008 ,  G06F11/27

Abstract: Hardware processors and methods to perform self-monitoring diagnostics to predict and detect failure are described. In one embodiment, a hardware processor includes a plurality of cores, and a diagnostic hardware unit to isolate a core of the plurality of cores at run-time, perform a stress test on an isolated core, determine a stress factor from a result of the stress test, and store the stress factor in a data storage device.

Abstract translation: 描述了执行自我监视诊断以预测和检测故障的硬件处理器和方法。 在一个实施例中，硬件处理器包括多个核心，以及诊断硬件单元，用于在运行时间隔离所述多个核心的核心，在隔离的核心上执行压力测试，从所述核心的结果中确定压力因素 压力测试，并将应力因子存储在数据存储设备中。