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    BIAS-LESS TECHNIQUE FOR DESIGN OF A DIGITAL LINEAR VOLTAGE REGULATOR
    11.
    发明公开
    BIAS-LESS TECHNIQUE FOR DESIGN OF A DIGITAL LINEAR VOLTAGE REGULATOR 审中-公开

    公开(公告)号：US20240329677A1

    公开(公告)日：2024-10-03

    申请号：US18192440

    申请日：2023-03-29

    Applicant: Intel Corporation

    Inventor： Kosta Luria ,  Michael Zelikson ,  Lior Gil

    IPC: G05F1/575 ,  G05F1/565 ,  G05F1/59

    CPC classification number: G05F1/575 ,  G05F1/565 ,  G05F1/59

    Abstract: Embodiments herein relate to a Digital Linear Voltage Regulator (DLVR). The DLVR includes a set of power links which each includes many columns of power transistors. The columns can be turned on or off individually based on digital data from a main control circuit. Additionally, individual power links can be turned on or off based on monitoring of a dropout voltage of the set of power links and a drain-to-source resistance, Rds_on, of replica columns. An input voltage may be monitored as an alternative. The monitoring compensates for changes in Rds_on due to changes in an input voltage, Vin, which could otherwise result in unstable behavior. The DLVR can avoid the complexity and power losses of dynamic biasing of the control gate voltages of the transistors.

    DLVR-SUPPLIED LOGIC DOMAIN OPERATIONAL VOLTAGE OPTIMIZATION
    12.
    发明公开
    DLVR-SUPPLIED LOGIC DOMAIN OPERATIONAL VOLTAGE OPTIMIZATION 审中-公开

    公开(公告)号：US20230205242A1

    公开(公告)日：2023-06-29

    申请号：US17561054

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Lior Gil ,  Kosta Luria ,  Michael Zelikson ,  Vadim Goldenberg

    IPC: G05F1/563 ,  G05F1/56

    CPC classification number: G05F1/563 ,  G05F1/561

    Abstract: A supply voltage may be set using a local voltage regulator, such as a Digital Linear Voltage Regulators (DLVR). A DLVR may include a compensator, and the performance of the compensator may be affected by a dropout (DO) voltage. To improve the performance of a compensator, a number of compensator calculations may be pre-calculated to reduce the complexity of remaining real-time computations and enable compensator calculations to be completed within a single DLVR clock cycle. A DLVR may include a sense filter, and the DLVR transfer function (TF) may be modified using dynamic shaping of open loop gain and pole locations of a sense filter. The DO range associated with the DLVR TF may be changed according to a monitored DO(t) to reduce the sensitivity of a domain VMIN on dropout, which reduces power consumption, increases performance, and enables simplification of test flows.

    Methods and systems to control power gates during an active state of a gated domain based on load conditions of the gated domain
    13.
    发明授权
    Methods and systems to control power gates during an active state of a gated domain based on load conditions of the gated domain 有权

    公开(公告)号：US10955885B2

    公开(公告)日：2021-03-23

    申请号：US16299019

    申请日：2019-03-11

    Applicant: Intel Corporation

    Inventor： Michael Zelikson ,  Vjekoslav Svilan ,  Norbert Unger ,  Shai Rotem

    IPC: G06F1/00 ,  G06F1/26 ,  G06F1/3234 ,  G06F1/3287 ,  H03K17/687

    Abstract: Methods and systems to adjust a resistance between a supply grid and a power-gated grid during an active state of a power-gated circuitry in response to load changes in the circuitry to maintain a relatively consistent IR droop. Subsets of power gates (PGs) may be selectively enabled and disabled based on changes in a load factor, such as a voltage, which may be monitored at a gated power distribution grid and/or proximate to a transistor gate within the power-gated circuitry. The adjusting may be performed to minimize a difference between the monitored voltage and a reference, such as with successive approximation or CMS software. PG subsets may be distributed within one or more layers of an integrated circuit (IC) die and may be selectively enabled/disabled based on location. PGs may be embedded within lower layers of an integrated circuit (IC) die, such as within metal layers of the IC die.

    CHARGE-SAVING POWER-GATE APPARATUS AND METHOD
    16.
    发明申请
    CHARGE-SAVING POWER-GATE APPARATUS AND METHOD 审中-公开

    公开(公告)号：US20180241384A1

    公开(公告)日：2018-08-23

    申请号：US15958768

    申请日：2018-04-20

    Applicant: Intel Corporation

    Inventor： Shai Rotem ,  Norbert Unger ,  Michael Zelikson

    IPC: H03K17/00 ,  H03K17/687

    CPC classification number: H03K17/00 ,  H03K17/687 ,  H03K2217/0036 ,  H03K2217/0063

    Abstract: A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power-gate circuit even in cases where the duration of the idle mode may be short.

    EXPOSING CIRCUITRY FOR DIE TESTING
    20.
    发明申请
    EXPOSING CIRCUITRY FOR DIE TESTING 审中-公开

    公开(公告)号：US20190287868A1

    公开(公告)日：2019-09-19

    申请号：US15921931

    申请日：2018-03-15

    Applicant: Intel Corporation

    Inventor： Michael Zelikson

    IPC: H01L21/66 ,  H01L23/50 ,  H01L23/528 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00

    Abstract: Disclosed herein are structures and techniques for exposing circuitry in die testing. For example, in some embodiments, an integrated circuit (IC) die may include: first conductive contacts at a first face of the die; second conductive contacts at a second face of the die, wherein the second face is opposite to the first face; circuitry; and a switch coupled between the second conductive contacts and the circuitry, wherein the circuitry is not electrically exposed by the second conductive contacts when the switch is open, and the circuitry is electrically exposed by the second conductive contacts when the switch is closed.

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