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公开(公告)号：US10156859B2
公开(公告)日：2018-12-18
申请号：US14129860
申请日：2013-09-26
Applicant: Intel Corporation
Inventor： Kosta Luria , Alexander Lyakhov , Joseph Shor , Michael Zelikson
Abstract: Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.
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公开(公告)号：US20180307257A1
公开(公告)日：2018-10-25
申请号：US16011260
申请日：2018-06-18
Applicant: Intel Corporation
Inventor： Kosta Luria , Alexander Lyakhov , Joseph Shor , Michael Zelikson
CPC classification number: G05F1/56 , G06F1/266 , H02M1/088 , H02M2001/0045
Abstract: Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.
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公开(公告)号：US09996143B2
公开(公告)日：2018-06-12
申请号：US15081639
申请日：2016-03-25
Applicant: Intel Corporation
Inventor： Joseph Shor
CPC classification number: G06F1/3287 , G06F1/26 , G06F1/28 , G06F1/3203 , G06F1/3206 , G06F1/3293 , G06F1/3296 , G06F17/5045 , H03K17/302 , Y02D10/171 , Y02D10/172 , Y02D50/20
Abstract: A disable module may be coupled to an analog circuit of an electronic circuit. The disable module may detect an input voltage that is supplied to the analog circuit, and may disable (such as by powering off) the analog circuit if the input voltage is below a reference value. The reference value may be set at a voltage level at or below a maximum voltage that may be present across a transistor in the analog circuit. Accordingly, the analog circuit may be disabled without damage to the transistors of the analog circuit. The disable module may detect whether the input voltage is below the reference value level by comparing the input voltage to a reference voltage. The electronic circuit may include a voltage regulator, and the voltage regulator may include the analog circuit.
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公开(公告)号：US20160087641A1
公开(公告)日：2016-03-24
申请号：US14490358
申请日：2014-09-18
Applicant: INTEL CORPORATION
Inventor： Noam Familia , Avigdor Saksonov , Eyal Fayneh , Joseph Shor
CPC classification number: H03L7/0991 , H03B5/10 , H03K3/0315 , H03L5/00 , H03L7/083 , H03L7/091 , H03L7/093 , H03L7/095 , H03L7/099 , H03L7/0995 , H03L7/18
Abstract: Some embodiments include apparatuses and methods having a digitally controlled oscillator (DCO) in a digital phase-locked loop (PLL) and a control loop. The DCO can generate an output signal having a frequency based on a value of a digital information. The control loop can adjust a value of a supply voltage of the DCO based on the value the digital information. Additional apparatuses and methods are described.
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Patent Agency Ranking
公开(公告)号：US10852756B2
公开(公告)日：2020-12-01
申请号：US16011260
申请日：2018-06-18
Applicant: Intel Corporation
Inventor： Kosta Luria , Alexander Lyakhov , Joseph Shor , Michael Zelikson
Abstract: Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.
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公开(公告)号：US20160269036A1
公开(公告)日：2016-09-15
申请号：US15161511
申请日：2016-05-23
Applicant: Intel Corporation
Inventor： Noam Familia , Avigdor Saksonov , Eyal Fayneh , Joseph Shor
CPC classification number: H03L7/0991 , H03B5/10 , H03K3/0315 , H03L5/00 , H03L7/083 , H03L7/091 , H03L7/093 , H03L7/095 , H03L7/099 , H03L7/0995 , H03L7/18
Abstract: Some embodiments include apparatuses and methods having a digitally controlled oscillator (DCO) in a digital phase-locked loop (PLL) and a control loop. The DCO can generate an output signal having a frequency based on a value of a digital information. The control loop can adjust a value of a supply voltage of the DCO based on the value the digital information. Additional apparatuses and methods are described.
Abstract translation: 一些实施例包括在数字锁相环（PLL）和控制环路中具有数字控制振荡器（DCO）的装置和方法。 DCO可以产生具有基于数字信息的值的频率的输出信号。 控制回路可以根据数字信息的值调节DCO的电源电压值。 描述附加的装置和方法。
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公开(公告)号：US20160209914A1
公开(公告)日：2016-07-21
申请号：US15081639
申请日：2016-03-25
Applicant: Intel Corporation
Inventor： Joseph Shor
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/26 , G06F1/28 , G06F1/3203 , G06F1/3206 , G06F1/3293 , G06F1/3296 , G06F17/5045 , H03K17/302 , Y02D10/171 , Y02D10/172 , Y02D50/20
Abstract: A disable module may be coupled to an analog circuit of an electronic circuit. The disable module may detect an input voltage that is supplied to the analog circuit, and may disable (such as by powering off) the analog circuit if the input voltage is below a reference value. The reference value may be set at a voltage level at or below a maximum voltage that may be present across a transistor in the analog circuit. Accordingly, the analog circuit may be disabled without damage to the transistors of the analog circuit. The disable module may detect whether the input voltage is below the reference value level by comparing the input voltage to a reference voltage. The electronic circuit may include a voltage regulator, and the voltage regulator may include the analog circuit.
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公开(公告)号：US09350365B2
公开(公告)日：2016-05-24
申请号：US14490358
申请日：2014-09-18
Applicant: Intel Corporation
Inventor： Noam Familia , Avigdor Saksonov , Eyal Fayneh , Joseph Shor
CPC classification number: H03L7/0991 , H03B5/10 , H03K3/0315 , H03L5/00 , H03L7/083 , H03L7/091 , H03L7/093 , H03L7/095 , H03L7/099 , H03L7/0995 , H03L7/18
Abstract: Some embodiments include apparatuses and methods having a digitally controlled oscillator (DCO) in a digital phase-locked loop (PLL) and a control loop. The DCO can generate an output signal having a frequency based on a value of a digital information. The control loop can adjust a value of a supply voltage of the DCO based on the value the digital information. Additional apparatuses and methods are described.
Abstract translation: 一些实施例包括在数字锁相环（PLL）和控制环路中具有数字控制振荡器（DCO）的装置和方法。 DCO可以产生具有基于数字信息的值的频率的输出信号。 控制回路可以根据数字信息的值调节DCO的电源电压值。 描述附加的装置和方法。
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公开(公告)号：US09866225B2
公开(公告)日：2018-01-09
申请号：US15161511
申请日：2016-05-23
Applicant: Intel Corporation
Inventor： Noam Familia , Avigdor Saksonov , Eyal Fayneh , Joseph Shor
IPC: H03L7/099 , H03L7/093 , H03L7/083 , H03K3/03 , H03L7/18 , H03L7/095 , H03L5/00 , H03B5/10 , H03L7/091
CPC classification number: H03L7/0991 , H03B5/10 , H03K3/0315 , H03L5/00 , H03L7/083 , H03L7/091 , H03L7/093 , H03L7/095 , H03L7/099 , H03L7/0995 , H03L7/18
Abstract: Some embodiments include apparatuses and methods having a digitally controlled oscillator (DCO) in a digital phase-locked loop (PLL) and a control loop. The DCO can generate an output signal having a frequency based on a value of a digital information. The control loop can adjust a value of a supply voltage of the DCO based on the value the digital information. Additional apparatuses and methods are described.
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