公开(公告)号：US20230420376A1

公开(公告)日：2023-12-28

申请号：US18462600

申请日：2023-09-07

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Debendra Mallik

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L25/18

CPC classification number: H01L23/5385 ,  H01L2224/17181 ,  H01L25/0652 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L21/4857 ,  H01L21/4853 ,  H01L21/481 ,  H01L25/18 ,  H01L2224/1703 ,  H01L2224/73253 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L25/0655

Abstract: Disclosed herein are microelectronic structures including bridges, and related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate with first and second metal layers; a cavity in the substrate, where a portion of the first and second metal layers, are exposed with the portion of the first metal layer partially overlapping the portion of the second metal layer; and a bridge component in the cavity, having a first conductive contact at a first face and a second conductive contact at a second face opposing the first face, the second face towards a bottom surface of the cavity, the portion of the first metal layer is between the second face of the bridge component and the portion of the second metal layer, and the second conductive contact is electrically coupled to the portion of the second metal layer in the cavity.

公开(公告)号：US11791274B2

公开(公告)日：2023-10-17

申请号：US16902777

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Jinhe Liu ,  Sairam Agraharam ,  Mohit Bhatia ,  Edvin Cetegen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/1703

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20250006678A1

公开(公告)日：2025-01-02

申请号：US18345437

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Harini Kilambi ,  Kimin Jun ,  Adel A. Elsherbini ,  John Edward Zeug Matthiesen ,  Trianggono Widodo ,  Adita Das ,  Mohit Bhatia ,  Dimitrios Antartis ,  Bhaskar Jyoti Krishnatreya ,  Rajesh Surapaneni ,  Xavier Francois Brun

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L25/065

Abstract: Disclosed herein are microelectronic assemblies, related apparatuses, and methods. In some embodiments, a microelectronic assembly may include a first die in a first layer; and a second and third die in a second layer, the second layer coupled to the first layer by hybrid bond interconnects having a first pad and a second pad, wherein the first pad is coupled to a first via in the second die and the first pad is offset from the first via by a first dimension, and the second pad is coupled to a second via in the third die and the second pad is offset from the second via by a second dimension different than the first dimension. In some embodiments, the first pad is offset from the first via in a first direction and the second pad is offset from the second via in a second direction different than the first direction.

公开(公告)号：US11887962B2

公开(公告)日：2024-01-30

申请号：US16902927

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Sairam Agraharam ,  Edvin Cetegen ,  Anurag Tripathi ,  Malavarayan Sankarasubramanian ,  Jan Krajniak ,  Manish Dubey ,  Jinhe Liu ,  Wei Li ,  Jingyi Huang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/30 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/17 ,  H01L2224/1703

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20240006358A1

公开(公告)日：2024-01-04

申请号：US17854813

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Zhihua Zou ,  Omkar Karhade ,  Botao Zhang ,  Julia Chiu ,  Vivek Chidambaram ,  Yi Shi ,  Mohit Bhatia ,  Mostafa Aghazadeh

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L2224/08059 ,  H01L2224/08145 ,  H01L2224/80031 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Bonding pedestals on substrates, and their manufacture, for direct bonding integrated circuit (IC) dies onto substrates. The electrical interconnections of one or more IC dies and a substrate are bonded together with the IC dies on and overhanging the pedestals. A bonding pedestal may be formed by etching down the substrate around the interconnections. A system may include one or more such pedestals above and adjacent a recessed surface on a substrate with IC dies overhanging the pedestals. Such a system may be coupled to a host component, such as a board, and a power supply via the host component.

公开(公告)号：US20230299049A1

公开(公告)日：2023-09-21

申请号：US17699028

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Nitin A. Deshpande ,  Omkar G. Karhade ,  Mohit Bhatia ,  Debendra Mallik

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/16 ,  H01L23/481 ,  H01L24/32 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/3128 ,  H01L21/565 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2224/32225 ,  H01L2224/16145 ,  H01L2224/0401

Abstract: A microelectronic component and a method of forming same. The microelectronic component includes: a first substrate having first through vias therein, the first substrate including silicon or glass; a first layer on a front surface of the first substrate and including one or more first dies coupled to the first through vias; a second substrate on a front surface of first layer and having second through vias therein and including silicon or glass; a second layer on a front surface of the second substrate, the first layer between the first substrate and the second substrate, the second layer including one or more second dies coupled to the second through vias; and electrically conductive structures on a back surface of the first substrate coupled to the first through vias.

公开(公告)号：US11735558B2

公开(公告)日：2023-08-22

申请号：US17740501

申请日：2022-05-10

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Anurag Tripathi ,  Takeshi Nakazawa ,  Steve Cho

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L24/30 ,  H01L23/5384 ,  H01L24/17 ,  H01L2224/1703

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20210391294A1

公开(公告)日：2021-12-16

申请号：US16902887

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Anurag Tripathi ,  Takeshi Nakazawa ,  Steve Cho

IPC: H01L23/00 ,  H01L23/538

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.