公开(公告)号：US20220102234A1

公开(公告)日：2022-03-31

申请号：US17033080

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Susmriti Das Mahapatra ,  Malavarayan Sankarasubramanian ,  Shenavia Howell ,  John Harper ,  Mitul Modi

IPC: H01L23/36 ,  H01L23/488 ,  H01L23/00 ,  H01L21/50 ,  H01L21/768

Abstract: An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10−6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

公开(公告)号：US12183688B2

公开(公告)日：2024-12-31

申请号：US17192770

申请日：2021-03-04

Applicant: Intel Corporation

Inventor： Valery Ouvarov-Bancalero ,  John Harper ,  Malavarayan Sankarasubramanian ,  Patrick Nardi ,  Bamidele Daniel Falola ,  Ravi Siddappa ,  James Mertens

IPC: H01L23/00 ,  H01L23/06 ,  H05K7/14

Abstract: A stiffener for an integrated circuit (IC) package assembly including an IC die electrically interconnected to a substrate. The stiffener is to be mechanically attached to the substrate adjacent to at least one edge of the IC die and have a coefficient of linear thermal expansion (CTE) exceeding that of the substrate. The stiffener may be an “anti-invar” metallic alloy. Anti-invar alloys display “anti-invar” behavior where thermal expansion of the material is significantly enhanced relative to other compositions of the particular alloy system. A package stiffener may be a high-Mn steel, for example, such as ASTM International A128. In other examples, a package stiffener is a MnCuNi, FeNiMn, or FeNiCr alloy having an average CTE over a range of 25-100° C. of at least 18 ppm, and a room temperature modulus of elasticity of at least 120 GPa.

公开(公告)号：US11335616B2

公开(公告)日：2022-05-17

申请号：US16498775

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Malavarayan Sankarasubramanian ,  Yongki Min ,  Ashay A. Dani ,  Kaladhar Radhakrishnan

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/522

Abstract: A semiconductor package may include a composite magnetic inductor that is formed integral with the semiconductor substrate. The composite magnetic inductor may include a composite magnetic resin layer and a plurality of conductive layers arranged such that the composite magnetic resin layer is interleaved between successive conductive layers. The resultant composite magnetic inductor may be disposed between dielectric layers. A core layer may be disposed proximate the composite magnetic inductor. A build-up layer may be disposed proximate the core layer or proximate the composite magnetic inductor in a coreless semiconductor substrate. A semiconductor die may couple to the build-up layer. The composite magnetic inductor beneficially provides a greater inductance than external inductors coupled to the semiconductor package.

公开(公告)号：US20240332112A1

公开(公告)日：2024-10-03

申请号：US18744108

申请日：2024-06-14

Applicant: Intel Corporation

Inventor： Susmriti Das Mahapatra ,  Malavarayan Sankarasubramanian ,  Shenavia Howell ,  John Harper ,  Mitul Modi

IPC: H01L23/36 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L23/488

CPC classification number: H01L23/36 ,  H01L21/4814 ,  H01L21/50 ,  H01L21/76838 ,  H01L23/367 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/488 ,  H01L23/562 ,  H01L2021/60135

Abstract: An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10−6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

公开(公告)号：US20220285288A1

公开(公告)日：2022-09-08

申请号：US17192770

申请日：2021-03-04

Applicant: Intel Corporation

Inventor： Valery Ouvarov-Bancalero ,  John Harper ,  Malavarayan Sankarasubramanian ,  Patrick Nardi ,  Bamidele Daniel Falola ,  Ravi Siddappa ,  James Mertens

IPC: H01L23/00 ,  H01L23/06 ,  H05K7/14

Abstract: A stiffener for an integrated circuit (IC) package assembly including an IC die electrically interconnected to a substrate. The stiffener is to be mechanically attached to the substrate adjacent to at least one edge of the IC die and have a coefficient of linear thermal expansion (CTE) exceeding that of the substrate. The stiffener may be an “anti-invar” metallic alloy. Anti-invar alloys display “anti-invar” behavior where thermal expansion of the material is significantly enhanced relative to other compositions of the particular alloy system. A package stiffener may be a high-Mn steel, for example, such as ASTM International A128. In other examples, a package stiffener is a MnCuNi, FeNiMn, or FeNiCr alloy having an average CTE over a range of 25-100° C. of at least 18 ppm, and a room temperature modulus of elasticity of at least 120 GPa.

公开(公告)号：US20210391295A1

公开(公告)日：2021-12-16

申请号：US16902927

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Sairam Agraharam ,  Edvin Cetegen ,  Anurag Tripathi ,  Malavarayan Sankarasubramanian ,  Jan Krajniak ,  Manish Dubey ,  Jinhe Liu ,  Wei Li ,  Jingyi Huang

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US12040246B2

公开(公告)日：2024-07-16

申请号：US17033080

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Susmriti Das Mahapatra ,  Malavarayan Sankarasubramanian ,  Shenavia Howell ,  John Harper ,  Mitul Modi

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/50 ,  H01L21/768 ,  H01L23/00 ,  H01L23/36 ,  H01L23/373 ,  H01L23/42 ,  H01L23/488 ,  H01L21/60

CPC classification number: H01L23/36 ,  H01L21/4814 ,  H01L21/50 ,  H01L21/76838 ,  H01L23/367 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/488 ,  H01L23/562 ,  H01L2021/60135

Abstract: An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10−6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

公开(公告)号：US11887962B2

公开(公告)日：2024-01-30

申请号：US16902927

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Sairam Agraharam ,  Edvin Cetegen ,  Anurag Tripathi ,  Malavarayan Sankarasubramanian ,  Jan Krajniak ,  Manish Dubey ,  Jinhe Liu ,  Wei Li ,  Jingyi Huang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/30 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/17 ,  H01L2224/1703

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20210098326A1

公开(公告)日：2021-04-01

申请号：US16498775

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Malavarayan Sankarasubramanian ,  Yongki Min ,  Ashay A. Dani ,  Kaladhar Radhakrishnan

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/522

Abstract: A semiconductor package may include a composite magnetic inductor that is formed integral with the semiconductor substrate. The composite magnetic inductor may include a composite magnetic resin layer and a plurality of conductive layers arranged such that the composite magnetic resin layer is interleaved between successive conductive layers. The resultant composite magnetic inductor may be disposed between dielectric layers. A core layer may be disposed proximate the composite magnetic inductor. A build-up layer may be disposed proximate the core layer or proximate the composite magnetic inductor in a coreless semiconductor substrate. semiconductor die may couple to the build-up layer. The composite magnetic inductor beneficially provides a greater inductance than external inductors coupled to the semiconductor package.