公开(公告)号：US09934164B2

公开(公告)日：2018-04-03

申请号：US15460977

申请日：2017-03-16

Applicant: INTEL CORPORATION

Inventor： Tomer Stark ,  Ron Gabor ,  Ady Tal ,  Joseph Nuzman

IPC: G06F11/00 ,  G06F12/14 ,  G06F12/02 ,  G06F11/07

CPC classification number: G06F12/1425 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0766 ,  G06F11/0772 ,  G06F11/0787 ,  G06F11/1666 ,  G06F12/0238 ,  G06F2201/80 ,  G06F2212/1032

Abstract: Memory corruption detection technologies are described. A system on a chip (SoC) may include a memory device and a memory controller. The memory device may store data from an application, wherein the memory device comprises a memory corruption detection (MCD) table. The memory controller may be coupled to the memory device. The memory controller may allocate a contiguous memory block in the memory and write a MCD word into the MCD table. The MCD word may include a write protection indicator that indicates a protection mode of a first portion of the contiguous memory block.

公开(公告)号：US20160283300A1

公开(公告)日：2016-09-29

申请号：US14668862

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ady Tal ,  Ron Gabor ,  Joseph Nuzman

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/10 ,  G06F11/1064

Abstract: Memory corruption detection technologies are described. A processor can include a memory to store data from an application, wherein the memory comprises a memory corruption detection (MCD) table. The processor can also include processor core coupled to the memory. The processor core can receive, from an application, a memory access request to access data of one or more contiguous memory blocks in a memory object of the memory. The processor core can also retrieve data stored in the one or more contiguous memory blocks based on the location indicated by the pointer. The processor core can also retrieve, from the MCD table, allocation information associated with the one or more contiguous memory blocks. The processor core can also send, to the application, a fault message when a fault event associated with the retrieved data occurs based on the allocation information.

Abstract translation: 描述了内存损坏检测技术。 处理器可以包括用于存储来自应用程序的数据的存储器，其中所述存储器包括存储器损坏检测（MCD）表。 处理器还可以包括耦合到存储器的处理器核心。 处理器核心可以从应用程序接收存储器访问请求以访问存储器的存储器对象中的一个或多个连续存储器块的数据。 处理器核还可以基于指示器指示的位置来检索存储在一个或多个连续存储器块中的数据。 处理器核心还可以从MCD表中检索与一个或多个连续存储器块相关联的分配信息。 当与检索到的数据相关联的故障事件基于分配信息发生时，处理器核心还可以向应用发送故障消息。

公开(公告)号：US20160259682A1

公开(公告)日：2016-09-08

申请号：US14635896

申请日：2015-03-02

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ady Tal ,  Ron Gabor

IPC: G06F11/10

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/10 ,  G06F11/1064

Abstract: Memory corruption detection technologies are described. A method can include receiving, from the application, an allocation request for an allocation of one or more contiguous memory blocks of the memory for a memory object. The method can further include allocating, by a processor, the one or more contiguous memory blocks for the memory object in view of a size of the memory object requested. The method can further include writing, into a MCD table, a first memory corruption detection (MCD) unique identifier associated with the one or more contiguous memory blocks. The method can further include creating a pointer with a memory address of the memory object and a second MCD unique identifier associated with the memory object. The method can further include sending, to the application, the pointer.

Abstract translation: 描述了内存损坏检测技术。 一种方法可以包括从应用程序接收用于存储器对象的存储器的一个或多个连续存储器块的分配的分配请求。 该方法可以进一步包括鉴于所请求的存储器对象的大小，由处理器分配用于存储器对象的一个​​或多个连续的存储器块。 该方法还可以包括将与该一个或多个连续存储器块相关联的第一存储器损坏检测（MCD）唯一标识符写入到MCD表中。 该方法还可以包括创建具有存储器对象的存储器地址的指针和与存储器对象相关联的第二MCD唯一标识符。 该方法还可以包括向应用发送指针。

公开(公告)号：US11693785B2

公开(公告)日：2023-07-04

申请号：US16728527

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Ron Gabor ,  Enrico Perla ,  Raanan Sade ,  Igor Yanover ,  Tomer Stark ,  Joseph Nuzman

IPC: G06F12/00 ,  G06F12/0895 ,  G06F12/1081 ,  G06F12/1009 ,  G06F12/0811 ,  G06F12/14 ,  G06F9/30 ,  G06F11/30

CPC classification number: G06F12/0895 ,  G06F9/30043 ,  G06F9/30101 ,  G06F11/3037 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/1466 ,  G06F2212/7207

Abstract: An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.

公开(公告)号：US11645135B2

公开(公告)日：2023-05-09

申请号：US17020663

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC: G06F11/07 ,  G06F12/00 ,  G06F9/38 ,  G06F12/109 ,  G06F21/60 ,  G06F12/14

CPC classification number: G06F11/0751 ,  G06F9/38 ,  G06F11/073 ,  G06F12/00 ,  G06F12/109 ,  G06F21/60 ,  G06F12/145 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/656

Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US11636049B2

公开(公告)日：2023-04-25

申请号：US17705857

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： David M. Durham ,  Ron Gabor

IPC: G06F21/00 ,  G06F12/14 ,  G06F21/60 ,  G06F21/62 ,  G06F21/57

Abstract: Embodiments are directed to memory protection with hidden inline metadata. An embodiment of an apparatus includes processor cores; a computer memory for the storage of data; and cache memory communicatively coupled with one or more of the processor cores, wherein one or more processor cores of the plurality of processor cores are to implant hidden inline metadata in one or more cachelines for the cache memory, the hidden inline metadata being hidden at a linear address level.

公开(公告)号：US11288213B2

公开(公告)日：2022-03-29

申请号：US16369880

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： David M. Durham ,  Ron Gabor

IPC: G06F21/00 ,  G06F12/14 ,  G06F21/60 ,  G06F21/62 ,  G06F21/57

Abstract: Embodiments are directed to memory protection with hidden inline metadata. An embodiment of an apparatus includes processor cores; a computer memory for the storage of data; and cache memory communicatively coupled with one or more of the processor cores, wherein one or more processor cores of the plurality of processor cores are to implant hidden inline metadata in one or more cachelines for the cache memory, the hidden inline metadata being hidden at a linear address level.

公开(公告)号：US11068339B2

公开(公告)日：2021-07-20

申请号：US16417555

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Ron Gabor ,  Hisham Shafi ,  Sergiu Ghetie ,  Mohan J. Kumar ,  Theodros Yigzaw ,  Sarathy Jayakumar ,  Neeraj S. Upasani

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07

Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US10649783B2

公开(公告)日：2020-05-12

申请号：US15143520

申请日：2016-04-30

Applicant: Intel Corporation

Inventor： Ido Ouziel ,  Lihu Rappoport ,  Robert Valentine ,  Ron Gabor ,  Pankaj Raghuvanshi

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/40

Abstract: A technique to enable efficient instruction fusion within a computer system is disclosed. In one embodiment, a processor includes multiple cores, each including a first-level cache, a fetch circuit to fetch instructions, an instruction buffer (IBUF) to store instructions, a decode circuit to decode instructions, an execution circuit to execute decoded instructions, and an instruction fusion circuit to fuse a first instruction and a second instruction to form a fused instruction to be processed by the execution circuit as a single instruction, the instruction fusion occurring when both the first and second instructions have been stored in the IBUF prior to issuance to the decode circuit, and wherein the first instruction was the last instruction to be stored in the IBUF prior to the second instruction being stored in the IBUF, such that the first and second instructions are stored adjacently in the IBUF.

公开(公告)号：US20190272214A1

公开(公告)日：2019-09-05

申请号：US16417555

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Ron Gabor ,  Hisham Shafi ,  Sergiu Ghetie ,  Mohan J. Kumar ,  Theodros Yigzaw ,  Sarathy Jayakumar ,  Neeraj S. Upasani

IPC: G06F11/10 ,  G06F11/07

Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.